De2 Verilog HDL LCD coding problem

Altera_Forum · ‎09-26-2015

Good day. we are currently doing a project using altera de2 that requires us to use the lcd. we have 3 .v files and VErilog3 is our top module.

 module Verilog3(    
    //////// CLOCK //////////
    CLOCK_50,
    
    //////// KEY //////////
    KEY,
    
    //////// LCD //////////
    LCD_BLON,
    LCD_DATA,
    LCD_EN,
    LCD_ON,
    LCD_RS,
    LCD_RW,
    );
    
    //=======================================================
//  PORT declarations
//=======================================================
//////////// CLOCK //////////
input                          CLOCK_50; 
//////////// KEY //////////
input                      KEY;
//////////// LCD //////////
output                        LCD_BLON;
inout                      LCD_DATA;
output                        LCD_EN;
output                        LCD_ON;
output                        LCD_RS;
output                        LCD_RW;
reg         Cont;
wire        DLY_RST;
assign    LCD_ON        =    1'b1;
assign    LCD_BLON        =    1'b1;    
always@(posedge CLOCK_50 or negedge KEY)
begin
    if(!KEY)
    Cont    <=    0;
    else
    Cont    <=    Cont+1;
end
    lcd_test             u0    (    
    
                            //    Host Side
                            
                            .iCLK       ( CLOCK_50 ),
                            .iRST_N     ( DLY_RST ),
                            
                            //    LCD Side
                            
                            .LCD_DATA ( LCD_DATA ),
                            .LCD_RW   ( LCD_RW ),
                            .LCD_EN     ( LCD_EN ),
                            .LCD_RS   ( LCD_RS )    ,
                            );
                            
endmodule

module    lcd_test (    //    Host Side                    iCLK,iRST_N,
                    //    LCD Side
                    LCD_DATA,LCD_RW,LCD_EN,LCD_RS    );
//    Host Side
input            iCLK,iRST_N;
//    LCD Side
output        LCD_DATA;
output            LCD_RW,LCD_EN,LCD_RS;
//    Internal Wires/Registers
reg        LUT_INDEX;
reg        LUT_DATA;
reg        mLCD_ST;
reg        mDLY;
reg            mLCD_Start;
reg        mLCD_DATA;
reg            mLCD_RS;
wire        mLCD_Done;
parameter    LCD_INTIAL    =    0;
parameter    LCD_LINE1    =    5;
parameter    LCD_CH_LINE    =    LCD_LINE1+16;
parameter    LCD_LINE2    =    LCD_LINE1+16+1;
parameter    LUT_SIZE    =    LCD_LINE1+32+1;
always@(posedge iCLK or negedge iRST_N)
begin
    if(!iRST_N)
    begin
        LUT_INDEX    <=    0;
        mLCD_ST        <=    0;
        mDLY            <=    0;
        mLCD_Start    <=    0;
        mLCD_DATA    <=    0;
        mLCD_RS        <=    0;
    end
    else
    begin
        if(LUT_INDEX<LUT_SIZE)
        begin
            case(mLCD_ST)
            0:    begin
                    mLCD_DATA    <=    LUT_DATA;
                    mLCD_RS        <=    LUT_DATA;
                    mLCD_Start    <=    1;
                    mLCD_ST        <=    1;
                end
            1:    begin
                    if(mLCD_Done)
                    begin
                        mLCD_Start    <=    0;
                        mLCD_ST        <=    2;                    
                    end
                end
            2:    begin
                    if(mDLY<18'h3FFFE)
                    mDLY    <=    mDLY+1;
                    else
                    begin
                        mDLY    <=    0;
                        mLCD_ST    <=    3;
                    end
                end
            3:    begin
                    LUT_INDEX    <=    LUT_INDEX+1;
                    mLCD_ST    <=    0;
                end
            endcase
        end
    end
end
always
begin
    case(LUT_INDEX)
    //    Initial
    LCD_INTIAL+0:    LUT_DATA    <=    9'h038;
    LCD_INTIAL+1:    LUT_DATA    <=    9'h00C;
    LCD_INTIAL+2:    LUT_DATA    <=    9'h001;
    LCD_INTIAL+3:    LUT_DATA    <=    9'h006;
    LCD_INTIAL+4:    LUT_DATA    <=    9'h080;
    //    Line 1    
    LCD_LINE1+0:    LUT_DATA    <=    9'h120;//    
    LCD_LINE1+1:    LUT_DATA    <=    9'h120;//
    LCD_LINE1+2:    LUT_DATA    <=    9'h120;//
    LCD_LINE1+3:    LUT_DATA    <=    9'h120;//
    LCD_LINE1+4:    LUT_DATA    <=    9'h153;// S
    LCD_LINE1+5:    LUT_DATA    <=    9'h169;// i
    LCD_LINE1+6:    LUT_DATA    <=    9'h167;// g
    LCD_LINE1+7:    LUT_DATA    <=    9'h16E;// n
    LCD_LINE1+8:    LUT_DATA    <=    9'h161;// a
    LCD_LINE1+9:    LUT_DATA    <=    9'h174;// t
    LCD_LINE1+10:    LUT_DATA    <=    9'h175;// u
    LCD_LINE1+11:    LUT_DATA    <=    9'h172;// r
    LCD_LINE1+12:    LUT_DATA    <=    9'h165;// e
    LCD_LINE1+13:    LUT_DATA    <=    9'h120;//
    LCD_LINE1+14:    LUT_DATA    <=    9'h120;//
    LCD_LINE1+15:    LUT_DATA    <=    9'h120;// 
    //    Change Line
    LCD_CH_LINE:    LUT_DATA    <=    9'h0C0;
    //    Line 2
    LCD_LINE2+0:    LUT_DATA    <=    9'h120;// 
    LCD_LINE2+1:    LUT_DATA    <=    9'h120;// 
    LCD_LINE2+2:    LUT_DATA    <=    9'h156;// V
    LCD_LINE2+3:    LUT_DATA    <=    9'h165;// e
    LCD_LINE2+4:    LUT_DATA    <=    9'h172;// r
    LCD_LINE2+5:    LUT_DATA    <=    9'h169;// i
    LCD_LINE2+6:    LUT_DATA    <=    9'h166;// f
    LCD_LINE2+7:    LUT_DATA    <=    9'h169;// i
    LCD_LINE2+8:    LUT_DATA    <=    9'h163;// c
    LCD_LINE2+9:    LUT_DATA    <=    9'h161;// a
    LCD_LINE2+10:    LUT_DATA    <=    9'h174;// t
    LCD_LINE2+11:    LUT_DATA    <=    9'h169;// i
    LCD_LINE2+12:    LUT_DATA    <=    9'h16F;// o
    LCD_LINE2+13:    LUT_DATA    <=    9'h16E;// n
    LCD_LINE2+14:    LUT_DATA    <=    9'h120;//
    LCD_LINE2+15:    LUT_DATA    <=    9'h120;//
    default:        LUT_DATA    <=    9'hxxx;
    endcase
end
LCD_Controller         u0    (    //    Host Side
                            .iDATA(mLCD_DATA),
                            .iRS(mLCD_RS),
                            .iStart(mLCD_Start),
                            .oDone(mLCD_Done),
                            .iCLK(iCLK),
                            .iRST_N(iRST_N),
                            //    LCD Interface
                            .LCD_DATA(LCD_DATA),
                            .LCD_RW(LCD_RW),
                            .LCD_EN(LCD_EN),
                            .LCD_RS(LCD_RS)    );
endmodule

module LCD_Controller (    //    Host Side                        iDATA,iRS,
                        iStart,oDone,
                        iCLK,iRST_N,
                        //    LCD Interface
                        LCD_DATA,
                        LCD_RW,
                        LCD_EN,
                        LCD_RS    );
//    CLK
parameter    CLK_Divide    =    16;
//    Host Side
input        iDATA;
input    iRS,iStart;
input    iCLK,iRST_N;
output    reg        oDone;
//    LCD Interface
output        LCD_DATA;
output    reg        LCD_EN;
output            LCD_RW;
output            LCD_RS;
//    Internal Register
reg            Cont;
reg            ST;
reg        preStart,mStart;
/////////////////////////////////////////////
//    Only write to LCD, bypass iRS to LCD_RS
assign    LCD_DATA    =    iDATA; 
assign    LCD_RW        =    1'b0;
assign    LCD_RS        =    iRS;
/////////////////////////////////////////////
always@(posedge iCLK or negedge iRST_N)
begin
    if(!iRST_N)
    begin
        oDone    <=    1'b0;
        LCD_EN    <=    1'b0;
        preStart<=    1'b0;
        mStart    <=    1'b0;
        Cont    <=    0;
        ST        <=    0;
    end
    else
    begin
        //////    Input Start Detect ///////
        preStart<=    iStart;
        if({preStart,iStart}==2'b01)
        begin
            mStart    <=    1'b1;
            oDone    <=    1'b0;
        end
        //////////////////////////////////
        if(mStart)
        begin
            case(ST)
            0:    ST    <=    1;    //    Wait Setup
            1:    begin
                    LCD_EN    <=    1'b1;
                    ST        <=    2;
                end
            2:    begin                    
                    if(Cont<CLK_Divide)
                    Cont    <=    Cont+1;
                    else
                    ST        <=    3;
                end
            3:    begin
                    LCD_EN    <=    1'b0;
                    mStart    <=    1'b0;
                    oDone    <=    1'b1;
                    Cont    <=    0;
                    ST        <=    0;
                end
            endcase
        end
    end
end
endmodule

unfortunately when we synthesize it with our board, the display is dark and the 2nd line of our text is not displayed unless a certain button is pushed. can anyone help me fix our problem?we are using quartus ii 13.0.

thanks in advance

Altera_Forum · ‎09-28-2015

I think you should use SignalTap II tool for debugging your problem.

Long.

Altera_Forum · ‎10-13-2015

The DLY_RST is not connected to anything at the top level. Maybe it should be driven by the Cont register?

Have you tried simulation? I think it is a simple state machine that you can validate its functions in modelsim. Note that the always for case LUT_INDEX is missing sensitivity list at the always.

Either become always @ (*) or always @ (LUT_INDEX)