AMBA architecture

Altera_Forum · ‎10-13-2015

Tell me whether this code is working as testbench for AHB protocol or not

module master;
  reg hready,hclk,hwrite;
  integer haddr={1,2,3,4,5,6,7,8,9,10};
  reg hrdata,hwdata;
  reg htrans;
  reg i; 
  parameter hsize=4;
  parameter idle=2'b00,
            busy=2'b01,
            non_seq=2'b10,
            seq=2'b11;
  initial
   begin
     hready=0;
     hclk=0;
     hwrite=0;
   forever# 10 hclk=~hclk;
   end
  
  
  initial
    begin
      htrans=2'b10;  //driving the transfer signal to nonsequential
      repeat(3)  # 10htrans=2'b11;//repeating 3 times sequential
    end
  
  always @(posedge hclk)
    begin
     hready=$random;// i have not designed slave so i am giving random values 
     hwrite=$random;
     
    end
  task address;
   
   for(i=0;i<=9;i=i+1)
    begin
  haddr=haddr+hsize;
    end
      endtask
   
task write;
   if(non_seq)
      begin
      wait(hready==1)
        if(hready==1 && hwrite==1)
      begin
        wait(hclk==1)
        hwdata=haddr;
    end
      else 
        hwdata=1'bx;
      end
  if(seq)
    begin
      wait(hready==1)
      if(hready==1 && hwrite==1)
      begin
        address;
      wait(hclk==1)
      hwdata=haddr;
      end
        else
        hwdata=1'bx;
    end
      endtask
task read;
  if(non_seq)
    begin
      wait(hready==1)
      if(hready==1 && hwrite==1)
        begin
      wait(hclk==1)
      hrdata=haddr;
    end
    else
    hrdata=1'bx;
    end
      if(seq)
    begin
      wait(hready==1)
      if(hready==1 && hwrite==1)
      begin
        address;
      wait(hclk==1)
      hrdata=haddr;
      end
        else
        hrdata=1'bx;
    end
 endtask
initial
  begin
    write;
    read;
  end
initial 
begin
$monitor("hclk=%d,hready=%d,hwrite=%d,hwdata=%d,hrdata=%d",hclk,hready,hwrite,hwdata,hrdata);
$dumpfile("master.vcd");
  $dumpvars(1,hclk,hready,haddr,hwdata,hrdata);
end
endmodule

In AHB protocol i have address and data . When i am testing that the address should get in one clock and the data should get after one clock period of address . Can any one tell me about this . please immediately.

if possible send me a test bench code for AHB protocol.for both master and slave.