Default port values in SystemVerilog

[Altera_Forum]

I am trying unsuccessfully to define a default value for an input port in a module definition, so that if an instantiation of it does not pass a value to that port, the default value is used without any error. According to Altera, Quartus 13 supports section 23.2.2 of the IEE standard 1800-2009 for SystemVerilog. On the Internet I found this reproduction of section 23.2.2.4 of the aforementioned standard, which I have included at the end of this posting. 

 When I try the syntax suggested below, I get a compiler error, even though I have chosen "SystemVerilog" as the version under Assignment: Settings. At first, I just assumed that this feature was not implemented by Altera, until I saw their page where they state that section 23.2.2 is supported by Quartus 13. Any thoughts? (I am a Verilog newbie, so be gentle.)   23.2.2.4 Default port values A module declaration may specify a default value for each singular input port. These default values shall be constant expressions evaluated in the scope of the module where they are defined, not in the scope of the instantiating module. The informal syntax to declare a default input port value in a module is as follows: module module_name ( ..., [ input ] [ type ] port_identifier = constant_expression, ... ) ; Defaults can be specified only for input ports and only in ANSI style declarations. When the module is instantiated, input ports with default values can be omitted from the instantiation, and the compiler shall insert the corresponding default values. If a connection is not specified for an input port and the port does not have a default value, then, depending on the connection style (ordered list, named connections, implicit named connections, or implicit .* connections), the port shall either be left unconnected or result in an error, as discussed in 23.3.2.1 through 23.3.2.4.

[Altera_Forum]

It would help us greatly if you showed a small example code with the exact error message you are getting. Also, does the file have a *.sv filename?

[Altera_Forum]

--- Quote Start ---  It would help us greatly if you showed a small example code with the exact error message you are getting. Also, does the file have a *.sv filename?  --- Quote End ---    Here is the relevant portion of my code, with an attempt to make the reset_n port optional by means of giving it a default value. Following the code, I am posting the error message.  module ncntupdn (  input [N-1:0]data_in,  input reset_n = 1,  input load,  input up,  input enp,  input clk,   output reg [N-1:0]count,  output wire rco_n,  output wire xrco_n // Acts just like rco_n except it is not disabled by enp going low );    parameter N = 4;   Error (10231): Verilog HDL error at ncntupdn.sv(10): value cannot be assigned to input "reset_n"   BTW, it didn't make any difference if the file was .v or .sv. Thanks for any advice.

[Altera_Forum]

Hi, 

 it makes a difference when you are using Aldec Riviera Pro , it gives an error when you are using Systemverilog statements inside a *.v file.  Regarding your default assignment. I think it's not allowed to assign an input port any value.   see "http://www.eda.org/sv-bc/hm/att-0595/01-port_connection_rules.pdf" for Systemverilog port connection rules.   Kr, Florian

[Altera_Forum]

--- Quote Start ---  Hi,  it makes a difference when you are using Aldec Riviera Pro , it gives an error when you are using Systemverilog statements inside a *.v file.  Regarding your default assignment. I think it's not allowed to assign an input port any value.   see "http://www.eda.org/sv-bc/hm/att-0595/01-port_connection_rules.pdf" for Systemverilog port connection rules.   Kr, Florian  --- Quote End ---     Thank you for your response. I will keep it in mind to always use .sv extension for compatibility with all tools.  I noticed that the pdf file you referenced is dated 06-Mar-2003, so I don't expect it to reflect an enhancement that was added to SystemVerilog in 2009. The enhancement I refer to is the ability to assign a default value to a port left unconnected (rather than have that default be determined merely by the data type, which was the case in 2003). I don't know if I have made a mistake in entering this default value (which seems pretty straightforward in the 2009 documentation), or if Altera is mistaken when they say that Quartus 13.0 supports this section of the SystemVerilog 2009 standard that adds this capability. Perhaps there is something in another section of the 2009 standard that restricts this ability in some way; I don't have access to the standard other than the small section I found online that seemed relevant to my needs.

[Altera_Forum]

You all should be using the ieee 1800-2012 lrm (http://go.mentor.com/get-1800). It's freely available, so there's no excuse for continuing to use other forms. 

 I can see from the error message that the file has a *.sv extension. I would replace reg with logic to confirm it recognizing SystemVerilog. If it recognizes logic, but not the default assignment, then it has a problem with supporting default assignments.