Delay between modules

[Altera_Forum]

Hi guys, 

 I am working on a project that has 2 modules connected in the design. I'd like to place an intentional delay between the lines that connect the two modules, how can I do this?   I have searched the forum already but was unsuccessful at finding a solution.  -JV

[Altera_Forum]

you could use a N taps shift register. It delays for N/f_clk s. f_clk is clock frequency.

[Altera_Forum]

Thanks for the reply Parrado. I need to delay for a certain amount of time, ie 2ns...I want to synthesize with delays added and see the new max frequency, so I'm not sure if your solution will work. 

 -JV

[Altera_Forum]

--- Quote Start ---  Thanks for the reply Parrado. I need to delay for a certain amount of time, ie 2ns...  --- Quote End ---    There is no reliable way to implement analog asynchronous delays inside an FPGA, if that's what you mean.  It is not totally impossible, you can use dummy combinational gates, and also force artificially long routing. But neither the hardware neither the tools were designed for this purpose.

[Altera_Forum]

--- Quote Start ---  There is no reliable way to implement analog asynchronous delays inside an FPGA, if that's what you mean.  It is not totally impossible, you can use dummy combinational gates, and also force artificially long routing. But neither the hardware neither the tools were designed for this purpose.  --- Quote End ---    Ah, I see vj, thank you. My next question would be...can I find out the delay of a combinational gate? Let's say I want to use NAND gates to model the delay, how could I find out the delay of that particular NAND gate used in quartus?  Also, I saw this thread: http://www.alteraforum.com/forum/showthread.php?t=3068  For that method in that thread, can I do this between two modules? I notice for that design that Rysc uploaded he used purely a BDF file, but I only have 2 Verilog files.  Thank you so much guys.  -JV

[Altera_Forum]

In the said thread (and many others as well) different methods to implement logic cell delay have been discussed, also using Verilog. Their limitation has been already mentioned. 

 Generally you can trust in the compiler tools' capability to arrange the existing routing delays in a way to achieve the intended timing, assuming your design uses a reasonable clocking scheme or you defined respective timing constraints.  In a typical synchronous design, the data path delay limits the number of logic or arithmetic operations that can be chained between two registers operated by the same clock, so you would be interested to reduce the delay rather than adding more.

[Altera_Forum]

FvM, I understand how synchronous circuits work, however I am introducing delay for a very specific reason. I want to see how much delay needs to be added to another path (not the critical path) in order for it to become the new critical path. Does that make sense? 

 -JV

[Altera_Forum]

--- Quote Start ---  FvM, I understand how synchronous circuits work, however I am introducing delay for a very specific reason. I want to see how much delay needs to be added to another path (not the critical path) in order for it to become the new critical path. Does that make sense?  -JV  --- Quote End ---    Hi,  why do you want to do that ? Do you want to know how large your positive slack on the path is ?  Kind regards  GPK

[Altera_Forum]

The advanced synthesis cookbook dicusses techniques to generate logic cell delays. 

http://www.altera.com/literature/manual/stx_cookbook.pdf

[Altera_Forum]

--- Quote Start ---  The advanced synthesis cookbook dicusses techniques to generate logic cell delays. http://www.altera.com/literature/manual/stx_cookbook.pdf  --- Quote End ---    I will take a look at that, thanks FvM.     --- Quote Start ---  Hi,  why do you want to do that ? Do you want to know how large your positive slack on the path is ?  Kind regards  GPK  --- Quote End ---    Hi GPK, Yes that is exactly what I want to do. I know a path in the circuit that is between the two modules that is not the critical path, and I want to find out what the slack is between that path and the critical path. Is this functionality already available and I dont know about it?  -JV

[Altera_Forum]

--- Quote Start ---  I will take a look at that, thanks FvM.     Hi GPK, Yes that is exactly what I want to do. I know a path in the circuit that is between the two modules that is not the critical path, and I want to find out what the slack is between that path and the critical path. Is this functionality already available and I dont know about it?  -JV  --- Quote End ---    Hi JV,  yes, you should find this information in the results of the timing analysis.  Kind regards  GPK