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I am using Quartus II 8.0 for programming a Cyclone III device. I have 2 LVDS clocks (fclk and lclk) an an 8 channel (12 bit) LVDS input that I wish to deserialize.
The megafunction for deserialization does not work for 12 bit data. Will I program my component in VHDL to deserialize in 12 bits, or can I use some other components to make this (DDIO, multiplex,DFF...) ? I'm using SOPC Builder. thanksLink Copied
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I can share a simple deserializer utilizing DDIO:
chan:
FOR I IN 0 TO 7 GENERATE
lvds_rcv : altddio_in
GENERIC MAP (
intended_device_family => "Cyclone III",
invert_input_clocks => "ON",
lpm_type => "altddio_in",
power_up_high => "OFF",
width => 1)
PORT MAP (
datain => AD9222_D(I TO I),
inclock => fastclock,
dataout_h => dataout_h(I DOWNTO I),
dataout_l => dataout_l(I DOWNTO I));
PROCESS (fastclock)
BEGIN
IF rising_edge(fastclock) THEN
lvds_sr(I) <= lvds_sr(I)(9 downto 0) & dataout_l(I) & dataout_h(I);
END IF;
END PROCESS;
PROCESS (slowclock)
BEGIN
IF reset = '1' THEN
lvds_rx(I) <= (others => '0');
ELSIF rising_edge(slowclock) THEN
lvds_rx(I) <= lvds_sr(I);
END IF;
END PROCESS;
END GENERATE;
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i believe you can type 12 into the MegaWizard even though it doesn't have a pull down for this value.
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Yes, that's true, if I remember right. I have my own deserializer, because I don't like the restrictions in phase setup of the "soft" LVDS MegaFunction and the strange RTL it offers for 14-Bit operation.
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Thank you people.
But, if I program my own deser, I will need to desenvolve a driver for Nios ( I need to run the program in Nios for interface with a memory). I need to edit a component of Mega Wizard and to try interface it, with a PIO for use it in Nios. If I use the altlvds component with 2 channels and factor 6 ( width 12), I will have physically two inputs, and I need connect both in a same entrance, how I made this with no error in quartus ?- Mark as New
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Factor 6 isn't correct. As thepancake suggested, you can simply type in a factor of 12 in the MegaWizard setup

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