Design Being Removed

[Altera_Forum]

Hi, 

 When I synthesize my design solely, the report is fine. But when I put it in an SOPC built design, only the top module which has only two pins (clock and a key) is left after synthesis. To be exact, report says number of logic elements used is "zero"! Does this mean because the design has no output in terms of pins, is being removed?! So how come I don't see any warning or info messages about it?! I'd really appreciate any help. Thanks,  Kaveh

[Altera_Forum]

If you don't have any output ports, then the design gets synthesized away. (How would the design do anything if it never tells anyone what it's doing)? That beings said, you should get a lot of messages in analysis and synthesis about registers being removed. The only thing I can think is you may be suppressing this messages(alond the messages tabs there is one for suppressed messages.) I've seen tons of logic get removed, but I always see messages about it. (The generat complaint is that there are to many messages, hence the suppression manager).

[Altera_Forum]

Thanks for the info. Actually, you're right, I changed the message level to 3 and now see the removal messages. So, now my question is, is there a way to ask the synthesizer not to remove them?! The reason I need this is because even if I send out some data lines as PINs, still some parts are being removed which shouldn't. Thanks again, 

 Kaveh

[Altera_Forum]

If they don't drive anything, how do you know they are being removed? (I'm being facetious, but you get the point. If a tree falls in the woods and no one hears it, if a design exists but there are no outputs...) 

 There are some constraints you can apply to keep logic, but there's the more fundamental problem of what you're trying to do.

[Altera_Forum]

I see the point. I think I'm going to make an output of some sort :) Thanks for the help, 

 Kaveh