Design partition with HSSI and DDR IPs

[JoEl]

Hello,

We starting with new project on Arria 10 GX 900 to 1150. Project is basically video switching matrix so many transcievers are used. I want to devide it to partitions to cut compilation time for components but I am not able to place NATIVE PHY out of root partition - compiler says:

Error(19733): The following instances of HSSI Transceiver periphery IP are not in the root partition. Remove any instances of this IP in a non-root partition.  

Error(19733): The following instances of External Memory interface periphery IP are not in the root partition. Remove any instances of this IP in a non-root partition.

So nor NATIVE PHY nor EMIF can't be out of root.

So I decided to lock main design and add features around of it, but when I select it as partition, same warning pops out. What am I doing wrong ? did I missed something here ?

How can I make partiton from ie. HDMI Intel core from example?

Best regards,

Josef

[Kenny_Tan]

May I know which version of Quartus you are using? Quartus Pro or Quartus Standard? As each of them have a different flow.

[JoEl]

Sure, we do use Quartus Pro 19.1.0 Build 240

So partition selection and LogiLock design implementation have different flow? Interesting, can you describe differences?

[Kenny_Tan]

Yes, if you are using std, you do not need to separate out the design partition for root and core.

If you are using Pro, you will need to separate out this two partition. For your case, you can follow the tutorial mention here:

https://www.intel.com/content/www/us/en/programmable/documentation/lyx1569936504360.html

But you need to upgrade your design to Q19.3. remember to back up your design before upgrade.