Design requires too many ram resources to fit in the selected device

[Altera_Forum]

Hello, 

 I have a design on verilog code that contains many modules. 4 modules represent ROM blocks (16 x 32-bit) that has 4-bit address, 32-bit data out. So each ROM block is 512 bits with a total of 2,048 bits.  the total number of memory bits used in the design is 327,680 bits (modules is used many times in the design). Although I have tried to fit my design in Cyclone III and Stratix III which has more available memory bits than what is required by the design .. I got an error "Design requires too many ram resources to fit in the selected device".  Please HELP!! Thanks

[Altera_Forum]

This is usually a result of the designer using the ram blocks inefficiently. If each of these takes a ram block, thats 9k bits per ram. And even the largest S3 part only has 1000 M9Ks. From your description, Im guessing you are using the rams highly inefficiently. 

 Without any code, it's difficult to see what you're doing.

[Altera_Forum]

Review the fitter resource utilization reports. What you'll possibly find is that each of your 16x32 ROM are consuming (1) M9K block, using (4) blocks with capacity >32,000 bits even though you're only using 2,048 of them. i.e. your design doesn't map efficiently to the available hardware resources and you may need to rethink some things. 

 http://www.altera.com/literature/hb/cyc3/cyc3_ciii51004.pdf

[Altera_Forum]

module block1(addr, clk, out); 

  input [3:0] addr;  input clk;  output [31:0] out;    (* romstyle = "M9K" *) reg [31:0] out;  // assigning values using always block and case statement  endmodule    this is the code for the one of the ROM blocks.

[Altera_Forum]

--- Quote Start ---  This is usually a result of the designer using the ram blocks inefficiently. If each of these takes a ram block, thats 9k bits per ram. And even the largest S3 part only has 1000 M9Ks. From your description, Im guessing you are using the rams highly inefficiently.  Without any code, it's difficult to see what you're doing.  --- Quote End ---     after several tries, I got my design to fit on Stratix III but the fitter summary shows that the number of block memory bits used is zero!! Although I am using the following verilog code for each ROM block:  module Block1(addr, clk, out);    input [3:0] addr;  input clk;  output [31:0] out;    (* romstyle = "M9K" *) reg [31:0] out;    always @(posedge clk) // assign values to out using case statement   endmodule