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Hi,
This is my first post, hope I am doing things right I have come across a situation which completely challenges my understanding of how and when the evaluation of signals in a process takes place. The following snippit should explain my problem. By the way, i am using Quartus Prime and the target is a DE2-115 board. Thanks -- This was written to highlight a shortcoming in my understanding -- about when signals are evaluated. -- I expected the counter to only increment once the KEY input -- turns from a '1' to a '0' -- With KEY at a '1' level for some time, both KEY and PrevKEY will be at '1' levels. -- Suppose that after the most recent clock cycle KEY turns to a '0' -- At the next clock transition, surely KEY(0) will be a '0' and PrevKEY(0) would still be '1' -- This should produce a single increment of the counter ???? -- what actually happens is that PrevKEY is totally ignored -- the counter increments all the time while the key is a '0' library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity Try is port ( CLOCK_50 : in std_logic; -- Generated by DE2 board KEY : in std_logic_vector(3 downto 0); -- Four pushbutton keys on De2-115 board LEDR : out std_logic_vector(17 downto 0) -- a group of red LEDs on the De2 board ); end try; architecture rtl of try is -- signal Counter : integer range 0 to 7 := 0; -- I tried using an integer did not work either signal Counter : std_logic_vector(2 downto 0); -- and also a std-logic_vector signal PrevKEY : std_logic_vector(3 downto 0); -- this holds the previous value of the four keys begin process(CLOCK_50) begin if rising_edge(CLOCK_50) then if KEY(0) <= '0' and PrevKEY(0) <= '1' then Counter <= Counter + 1; end if; PrevKEY <= KEY; end if; end process; -- LEDR(2 downto 0) <= std_logic_vector(to_unsigned(Counter, 3)); -- this was when I tried the integer LEDR(2 downto 0) <= Counter; end rtl;Link Copied
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Because you have used <= (less than or equal) in your compare, it is comparing a single bit to a single bit with a less than doesnt really mean much. KEY(0) <= '0' is always true when KEY = '0', and PrevKey <='1' is true when PrevKey is '0' or '1', so the equation can be reduced to:
if key(0) = '0' then
counter <= counter + 1;
end if;
PS. Have you debounced your keys elsewhere? you may get several increments of counter without debouncing the key presses. As a beginner, I also recommend you get into the habit of not using std_logic_unsigned. It is a non standard VHDL package. Numeric std is the real IEEE standard.
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Hi,
Thanks very much for your response. It was a typo on my side, I accidentally typed the "<=" when it was supposed to be just a "=', but I never noticed it, no matter how long I looked at my code. The reason I am using 4 keys as a vector is that they appear like that on the DE2-115 board and I was using the standard assignment file which came with the board. The KEY signals are electronically debounced on the DE2 board. Thanks too for the reminder about NUMERIC_STD. Will always use that in future. Regards Stephen
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