Determining toggle rate for the power estimate

[Altera_Forum]

I need to determine toggle rate for the power estimate of a new FPGA design.  

Simulation VCD is not available. It's a very large design, and simply using default 12.5% is not going to work - I need much more accurate results.  Are there any methods or "rule of thumb" to come up with a realistic toggle rate range.  Thanks, Evgeni

[Altera_Forum]

Ah, the Holly Grail of PSU design for FPGAs... 

 I don't think there is anything absolute here below. Simply some observations/analysis from some quantitative data we collected following experiments some time ago. We were asking ourselves the same question.  In short we found we could rely - reasonably well - on the power estimators. But that doesn't answer your question.  We performed some tests on a relatively simple FPGA board we had - Cyclone IV based. This board is essentially an I/O card that connects to other modules in the system but has relatively little on it except the FPGA and PSUs. Hence, we could pretty accurately determine the I/O loading, which was pretty small. We put a number FPGA designs together with various known (by design) toggle rates.  By taking power measurements from the board and plugging the appropriate numbers (including the known toggle rate) into the estimator we concluded that we could trust the power estimator for that particular FPGA design - give or take a margin of error we had, that we decided was pretty static. We concluded that we could estimate the toggle rate by working backwards from the power measurement.  We then put in part of (it wasn't targeted at this particular board) our real FPGA design. We judged it's toggle rate by working backwards from the power measurement.  We process video data for video conferencing equipment. Really boring (practically static) video, highly compressible. The block we tested worked on uncompressed data. We found we could change the toggle rate from: somewhere under 2% for a static colour across the screen; through 3% for a static picture; to around 5% for a typically boring video conference feed; right up to 14.5% for an action film. So a variance of over 700% based purely on the FPGA's input stimulus.  We've since used this technique to estimate toggle rates of entire FPGA designs on other platforms. We very rarely (perhaps never) conclude the average toggle rate across the device is over 12.5% for our designs.  If this is really critical to you then I'd suggest you consider repeating this experiment with portions of your code running on a platform where you can measure the power consumed by the FPGA. It'll give you a very good steer towards the answer you're after.  Cheers, Alex

[Altera_Forum]

Thanks Alex.  

That's what I thought intuitively: just measure the power on a working platform under different operating conditions, and correlate those with power estimates.  Then use that correlation model for similar designs.