Difference Equation in VHDL

[Altera_Forum]

Hello, I am using the kit DE0 - Nano that has a EP4CE22F17C6N FPGA, to control a multilevel converter. The code that I made works in open loop, showing that the PWMs channels are working. The code to get the values ​​of the A / D converter is also functioning. However, the closed-loop system does not work. Got difference equation of the controller with the aid of MATLAB. Simulating this difference equation in PSIM software, everything works great. Below is the Process I'm using to obtain the control signal. 

 rotina4: process (LiberaCalculo)    begin    if rising_edge (LiberaCalculo) then    EK2:= EK1;  UK2:= UK1;  EK1:= EK;  UK1:= UK;  EK:= ((senoComp - ValorAtual)*9);  UK:= ((K0*UK1 + K1*UK2 + K2*EK - K3*EK1 + K4*EK2)/1000);   end if; end process rotina4;  Where:  shared variable K0: integer :=624; shared variable K1: integer :=376; shared variable K2: integer :=2733; shared variable K3: integer :=5163; shared variable K4: integer :=2438; shared variable UK: integer :=0; shared variable UK1: integer :=0; shared variable UK2: integer :=0; shared variable EK: integer :=0; shared variable EK1: integer :=0; shared variable EK2: integer :=0;  Ps. The Originals coefficients are K0 = 0.624, K1 = 0.376, K2 = 2.733, K3 = 5.163 e K4 = 2.438. These coefficients were multiplied by 1000 to eliminate the values ​​to the decimal point and then performed the calculation, the result is divided by 1000. The senoComp variable receives values ​​ranging from -1900 to 1900 and ValorAtual also receives values ​​of this magnitude. Is there any tool in Quartus where I can see the values ​​of UK real time? What is error, I may be committing to the system does not work ?

[Altera_Forum]

Here is a map of your nodes: 

 ((senoComp - ValorAtual)*9) => EK => EK1 => EK2  k0*UK1 + k1*UK2 + k2*EK - k3* EK1 + k4*Ek2 => UK => UK1 => Uk2  all above are variables and hence wired directly, there might be some registers implied but too complicated to work out.  what is your original difference equation?  do not use variables, use signals so we can follow you. do not multiply five times/add/subtract without pipelining. do not divide by 1000 if you can, e.g. scale to 1024 then discard 10 lsbs.

[Altera_Forum]

Is liberacalculo a clock signal? Doesn't seem like it is, it should be. You also can't see variables in Quartus II software, only signals. 

Try to use signals instead of shared variables and multiply/divide by a value that is 2^N, so it's just a simple shift. This divide is probably not doing what you want it to.