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Different results with Quartus II 9.1 sp2 and Quartus II 7.2

Altera_Forum
Honored Contributor II
‎02-01-2011 04:40 PM
1,060 Views

I compiled an old verilog code (which was previously compiled with "Quartus II 7.2") with "Quartus II 9.1 sp2" and found different results.  

Specifically, some numbers treated as signed in 7.2 are being treated as unsigned in 9.1 sp2 though they are declared as signed. I have no idea what is happening!! 

can somebody help me??
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Altera_Forum
Honored Contributor II
‎02-01-2011 04:48 PM
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Is the simulation run in Modelsim in both cases?

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Altera_Forum
Honored Contributor II
‎02-01-2011 05:12 PM
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not simulation... we run the program in DE2 board, cyclone II FPGA.

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