Differential pins and clock constraints

[Altera_Forum]

I had a question about writing timing constraints for differential pins. I am constraing an interface between a Cyclone II and an AD9726 fast dac. The FPGA provides 16 differential data outputs along with a differential data clock to the DAC.  

 My constraints as of now are (CLK_100MHZ is clock input to FPGA):  create_generated_clock -name FDAC1_DCKIN -source [get_ports {CLK_100MHZ}] [get_ports {FDAC1_DCKIN}]  set_output_delay -clock FDAC1_DCKIN -min 0.000 [get_ports {FDAC1_D [*]*}] set_output_delay -clock FDAC1_DCKIN -max 0.000 [get_ports {FDAC1_D [*]*}]  The first problem I had was timequest reporting that all the complement data pins, FDAC1_D [*](n), were not constrained. I fixed this by adding the extra '*' to FDAC1_D [*].  But how do I constrain the differential clock FDAC1_DCKIN? I tried creating a generated clock that applied to both FDAC1_DCKIN and FDAC1_DCKIN(n) but timequest complained no paths existed. Anyone have experience with this?

[Altera_Forum]

You have constrained your DAC data with respect to DAC clk. That is enough. 

The DAC clock itself can be set as false path because what matters is data relation to clk. I note you have put zero delay. Normally you put +tSU and -tH of DAC(plus board effect) unless DAC does not need these constraints. In that case you will target minimum data skew (I suggest +50 ps, -50 ps instead of zeros).