Do we need to manually Pin map HBM m2u Interface ports

[SivaKona]

Critical Warning (12677): No exact pin location assignment(s) for 40 pins of 72 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report

Getting following Critical Warning in fit.plan.rpt

The un-mapped 40 pins are the following m2u interface ports exported from HBM controller instances 

///// HBM m2u bridge signals /////
input wire hbm_b_m2u_bridge_cattrip, // hbm_b_m2u_bridge.cattrip
input wire [2:0] hbm_b_m2u_bridge_temp, // .temp
input wire [7:0] hbm_b_m2u_bridge_wso, // .wso
output logic hbm_b_m2u_bridge_reset_n, // .reset_n
output logic hbm_b_m2u_bridge_wrst_n, // .wrst_n
output logic hbm_b_m2u_bridge_wrck, // .wrck
output logic hbm_b_m2u_bridge_shiftwr, // .shiftwr
output logic hbm_b_m2u_bridge_capturewr, // .capturewr
output logic hbm_b_m2u_bridge_updatewr, // .updatewr
output logic hbm_b_m2u_bridge_selectwir, // .selectwir
output logic hbm_b_m2u_bridge_wsi, // .wsi

input wire hbm_t_m2u_bridge_cattrip, // hbm_t_m2u_bridge.cattrip
input wire [2:0] hbm_t_m2u_bridge_temp, // .temp
input wire [7:0] hbm_t_m2u_bridge_wso, // .wso
output logic hbm_t_m2u_bridge_reset_n, // .reset_n
output logic hbm_t_m2u_bridge_wrst_n, // .wrst_n
output logic hbm_t_m2u_bridge_wrck, // .wrck
output logic hbm_t_m2u_bridge_shiftwr, // .shiftwr
output logic hbm_t_m2u_bridge_capturewr, // .capturewr
output logic hbm_t_m2u_bridge_updatewr, // .updatewr
output logic hbm_t_m2u_bridge_selectwir, // .selectwir
output logic hbm_t_m2u_bridge_wsi // .wsi

Do we really need to map these ports to FPGA IO Pins ?

How can I fix this Critical Warning?

Regards

Siva Kona

[ShengN_Intel]

Hi Siva Kona,

In order to eliminate the Critical Warning (12677): No exact pin location assignment(s). You should assign locations to the pins listed above by Pin Planner, Assignment Editor under ''Assignments'' tab or TCL console.

Best regards,
Sheng

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

[SivaKona]

Hi Sheng,

Thanks for the reply.

HBM m2u bridge conduit interface connects to inbuilt HBM PHY. Right?

Are there any specific Pin locations that HBM m2u ports must be mapped to? 

Regards

Siva Kona

[ShengN_Intel · Accepted solution]

Hi Siva Kona,

Right. HBM m2u bridge conduit interface are connected to inbuilt HBM PHY. There is nothing to do with the FPGA IO pins so you can just leave the ports and ignore the warning. Those ports will be connected externally.

If you want to do some simulation on this HBM controller instances (HBM m2u), you can also just ignore the critical warning as it'll not affect the result as long as there is no error.

However if you want to simulate HBM m2u connected to HBM PHY, you should make sure the ports of both instances are connected properly.

Hope it helps.

Best regards,
Sheng

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

[ShengN_Intel]

Hi Siva Kona,

I’m glad that your issue has been resolved.
I'll now transition this thread to community support.
If you have a new question, feel free to open a new thread to get the support from Intel experts. 

Thank you.

Best regards,
Sheng

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.