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Does Power consumption depend completly on accelerator architecture design?


I have designed an accelerator on arria 10 FPGA using OpenCL. I am using around 37% logic, 95%BRAM, 37%DSP. When I run the power monitor tool and check VCC, VCCRT_GXB, VCCPT power rails (most of the power contributed in these rails), I see no change in the power curve.


When I program higher logic utilization based design, then my power consumption increases which is understandable. But I dont see changes in the power curve while the application is running. My Kernels have several DRAM accesss and multiplication operations. I was hoping that they would contribute to some kind of dynamic power.


Does the power consumption in general depend only on the accelerator design?

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Valued Contributor III

The majority of the power consumption will be static power. For standard designs with low signal activity, dynamic power consumption will be less than 10 watts on Arria 10 while the static power consumption can go up to 30-40 watts depending on area utilization. However, you should still see a clear increase in power consumption when the application is running. My guess is that your kernel run time is probably too short for the increase in power consumption to show up in the monitoring tool; try to make sure your kernel is at least running for a few hundred milliseconds. I am not sure what the sampling frequency of the monitoring tool is.

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