Does Quartus support using a VHDL configuration as a top-level entity?

Altera_Forum · ‎07-31-2014

The question title says it all. I thought it would be pretty straightforward to do so, since Quartus already handles most of the configuration capabilities of VHDL, and this should be possible as specified in the language standard.

Anyway, here is some source code that demonstrates the issue. The problem is that the code compiles ok if I specify logic_function as the top-level entity, but it gives the following error if I specify logic_function_cfg as the top-level entity:

Error (12007): Top-level design entity "logic_function_cfg" is undefined

----------------------------------------
entity nand_gate is
    port (
        a, b: in bit;
        y: out bit
    );
end;
architecture dataflow of nand_gate is
begin
    y <= a nand b;
end;
----------------------------------------
entity xor_gate is
    port (
        a, b: in bit;
        y: out bit
    );
end;
architecture dataflow of xor_gate is
begin
    y <= a xor b;
end;
----------------------------------------
entity logic_function is
    port (
        a, b: in bit;
        y: out bit
    );
end;
architecture dataflow of logic_function is
    component gate_component is
        port (
            a, b: in bit;
            y: out bit
        );
    end component;
begin
    gate_instance: component gate_component
        port map (a => a, b => b, y => y);
end;
----------------------------------------
configuration logic_function_cfg of logic_function is
    for dataflow
        for gate_instance: gate_component
            use entity work.nand_gate;
        end for;
    end for;
end;
----------------------------------------

Altera_Forum · ‎07-31-2014

you still need logic_function as the top level, it must always be an entity at the top level to connect the pins. You then define the behaviour with the architecture, not the entity. so you would have multiple architectures for the same entity with different behaviours.

Honestly, configurations are hardly ever used. Many companies only allow 1 architecture per entity - if you want different behaviour define another entity.

Altera_Forum · ‎07-31-2014

Hi Tricky,

I understand that a configuration *has* pins, the same pins as the entity it configures.

The code in the example analyzes and elaborates without any problem, with the configuration as the top-level entity, in both ModelSim and GHDL. In ModelSim, I can see that it has the same pins as the entity it configures.

The problem with having several entities is that it would cause a lot of code duplication. I also hardly find any use for configurations, but in this case they would be a great help.

Thanks,

Altera_Forum · ‎07-31-2014

I'm not sure if this will help, but I recall that the the Oregano 8051 core (its free) uses configurations, and that there is an Altera DE2 example in the code-base (so Quartus has been used to synthesize the code).

You could see if their use of configurations matches your application.

Cheers,

Dave

Altera_Forum · ‎07-31-2014

Dave, thanks for the pointer, this is really interesting stuff. After looking into the project source code and instructables (http://www.oreganosystems.at/download/mc8051_cyclone_nios_designflow.pdf), I gather that in the Oregano 8051 design configurations are not to used for synthesis. Also, most of the synthesis process (at least everything that is vendor-agnostic) is done with Synplify Pro.

Seems to support the general idea that configurations are not much used for synthesis...

Thanks,

Altera_Forum · ‎07-31-2014

--- Quote Start ---

After looking into the project source code and instructables (http://www.oreganosystems.at/download/mc8051_cyclone_nios_designflow.pdf), I gather that in the Oregano 8051 design configurations are not to used for synthesis.

--- Quote End ---

I thought the memory interfaces were defined by configurations, i.e., generic memory for simulation and then device-specific memory for synthesis. Then again, perhaps they did something "special" to support the DE2 board.

--- Quote Start ---

Also, most of the synthesis process (at least everything that is vendor-agnostic) is done with Synplify Pro.

--- Quote End ---

I know I tested the core with Modelsim, but I thought I synthesized the DE2 design with Quartus ...

--- Quote Start ---

Seems to support the general idea that configurations are not much used for synthesis...

--- Quote End ---

I think its more that Quartus lacks the synthesis support (along with several other standard language features), so as the end-users we're forced to work within the constraints of the vendor tool :)

You could try Mentor's tools, eg., Precision or Leonardo, generate an EDIF netlist, and then synthesize that.

Cheers,

Dave