Dynamic array in Verilog

[Altera_Forum]

hello everyone 

I know that dynamic array is not supported in Verilog and Quartus. I want to know does anybody has an idea or algorithm to use instead of dynamic array. I mean I am searching for something that works instead of a dynamic array. thanks

[Altera_Forum]

What do you need a dynamic array for? Is this for an FPGA or for a test bench?

[Altera_Forum]

yes it is for FPGA.

[Altera_Forum]

And why do you need dynamic re-sizing?

[Altera_Forum]

Not that it's an algoirthm but memory would be a good candidate, just size the memory for the maximum dynamic range you think you'll need. We don't really know what you are trying to accomplish so our recommendations will be shots in the dark.

[Altera_Forum]

I am working on an adaptive filter that number of its coefficient is changeable. That is why I need dynamic re-sizing.

[Altera_Forum]

You better set coefficients to maximum case then assign zero to those redundant