ERROR 10482 std_ulogic not declared

Altera_Forum · ‎04-12-2010

I write a simple code by VHDL:

the top-level:

-- USE LIBRARY IEEE 1164
library IEEE;
use IEEE.std_logic_1164.all;
------------------------------------------------------------------------
entity A_gt_B is
    port(    inA, inB    :    in    std_ulogic;
            outC        :    out    std_ulogic;
            gt            :    in  std_ulogic);
end entity A_gt_B;
architecture A_gt_B_Behavior of A_gt_B is
    --conponent declaratrion
    component my_inv 
        port(    in1:    in std_ulogic;
                out1:    out std_ulogic);
    end component;
    component my_nand2 
        port(    in1,in2:    in std_ulogic;
                out1:    out std_ulogic);
    end component;
    component my_nand3 
        port(    in1,in2,in3:    in std_ulogic;
                out1:    out std_ulogic);
    end component;    
    --configuration specification
    FOR ALL:    my_inv use entity work.INV_gate(INV_behavior);
    FOR ALL:    my_nand2 use entity work.NAND2_gate(NAND2_behavior);
    FOR ALL:    my_nand3 use entity work.NAND3_gate(NAND3_behavior);
    --signal declaraion
    signal    g1_to_g3, g2_to_g5, g3_to_g5, g4_to_g5:    std_ulogic ;    
begin
BAR_B:        my_inv port map( inB, g1_to_g3);
A_NAND_B:    my_nand2 port map( inA, g1_to_g3, g2_to_g5);
BAR_B:        my_inv port map( inB, g1_to_g3);
A_NAND_B:    my_nand2 port map( inA, g1_to_g3, g2_to_g5);
B_NAND_GT:    my_nand2 port map( gt, g1_to_g3, g3_to_g5);
A_NAND_GT:    my_nand2 port map( inA, gt, g4_to_g5);
NAND3:        my_nand3 port map( g2_to_g5, g3_to_g5, g4_to_g5, outC);
end architecture A_gt_B_Behavior;

and the basic logic:

-- USE LIBRARY IEEE 1164
library IEEE;
--use IEEE.std_logic_1164.all;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- INV
entity INV_gate is
    port(    in1    :    in    std_ulogic;
            out1:    out    std_ulogic);
end entity INV_gate;
architecture INV_behavior of INV_gate is
begin
    out1 <= not in1 after 5ns;
    
end architecture INV_behavior;
------------------------------------------------------------------------
-- NAND2
entity NAND2_gate is
    port(    in1, in2:    in    std_ulogic;
            out1    :    out    std_ulogic);
end entity NAND2_gate;
architecture NAND2_behavior of NAND2_gate is
begin
    out1 <= in1 nand in2 after 5ns;
    
end architecture NAND2_behavior;
------------------------------------------------------------------------
-- NAND3
entity NAND3_gate is
    port(    in1, in2, in3    :    in std_ulogic;
            out1            :    out    std_ulogic);
end entity NAND3_gate;
architecture NAND3_behavior of NAND3_gate is
begin
    out1 <= not ( in1 and in2 and in3 )after 5ns;
    
end architecture NAND3_behavior;

when I compile it, it shows error message :

Error (10482): VHDL error at basic_logic.vhd(57): object "std_ulogic" is used but not declared

but in the first line I already declared the ieee library!

who can tell me why :(

p.s. Sorry, my English is a little weak > <

Altera_Forum · ‎04-13-2010

A VHDL compiler "forgets" about the included libraries between two entities or architectures (I don't remember which one). You must re-include the ieee library and ieee.std_logic_1164.all package before each entity.

It is usually recommended to put only one entity per file.

Is there a reason why you use the unresolved std_ulogic type instead of the more usual std_logic?

Altera_Forum · ‎04-13-2010

--- Quote Start ---

A VHDL compiler "forgets" about the included libraries between two entities or architectures (I don't remember which one). You must re-include the ieee library and ieee.std_logic_1164.all package before each entity.

It is usually recommended to put only one entity per file.

Is there a reason why you use the unresolved std_ulogic type instead of the more usual std_logic?

--- Quote End ---

There is one good reason - all multiple driver errors are picked up at compile time rather than elaboration. Ideally, everyone would use std_ulogic unless they were building a tri-state bus.

The problem is everyone uses std_logic and so to avoid all the type casting, we all stick to one thing.

Altera_Forum · ‎04-14-2010

Thanks for your answers!:)

I try to put " library ieee;" and " use ieee.std_logic_1164.all; " before every entities, and compile successed!

I started to learned VHDL recently, there are many different between VHDL and C/C++. In C/C++,it just includ library in the begin of code, but VHDL not. I was confused that did this problem just in QuartusII or in every VHDL compiler?

Anyway, thanks a lot!!