Early Pin Planning (without HDL)

[Altera_Forum]

Here's my question: When you are doing early design pin-planning (checking I/O assignments without any HDL files), how do you enter buses? For example, I have mybus[255..0] that I want to get into Quartus.  

 - I can use a handy text editor to directly edit the QSF, but 256 pins is a lot of times to write mybus[x] (even with cut & paste). - I can put mybus[0] into the "To" column in the assignment editor and drag the lower-right corner of the cell down 256 rows (Quartus will auto-increment), but I haven't found a nice way to add 256 empty rows into which I can drag these 256 "mybus" entries. - I can use the pin planner and create a group (Assignments -> Assignment (Time) Groups...) called mybus[255..0] and add mybus[255..0] as members of the group, but that messes up the pin planner and just shows 256 mybus lines in the "all pins" box but refusing to display a group called mybus[255..0] or assign any pins to the group. - In the pin planner, I can create a group called "foobar" and add mybus[255..0] to it. This almost works, creating 256 "mybus" entries in the "all pins" box and making them part of the "mybus" group, but it puts "mybus" as a sub-group of "foobar" in the "groups" box and won't treat "mybus" as a stand-alone group.   The desired behavior is to have Quartus allow me to enter "mybus[255..0]" as a group that I can assign I/O standards to and "reserve pin" assignments and still allow me access to individual "mybus[x]" pins (for location assignments). I want to get this without having to individually create 256 entries in the pin planner or assignment editor and without me having to write HDL yet.    I want to type "mybus[255..0]" somewhere in the Assignment Editor or the Pin Planner and end up with 256 lines in the QSF file that looks like:   set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to mybus[0] set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to mybus[1] ... set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to mybus[255]    (This is what you get if you start with HDL as your design input)   The best you can get in the pin planner ("mybus" as a sub-group under the "foobar" group as mentioned above) is actually not even close to that. The foobar example creates explicit assignment groups in the QSF:   set_global_assignment -name ASSIGNMENT_GROUP_MEMBER mybus[255..0] -section_id foobar   And although you can't create this in the pin planner, if you manually put:   set_global_assignment -name ASSIGNMENT_GROUP_MEMBER mybus[255..0] -section_id mybus[255..0]   in the QSF file, then the pin planner doesn't recognize this as a group to display in the "groups" box (but does prevent you from assigning any of the mybus[x] pins in the "all pins" box to any other group).   Arrrrg. Are you all just writing the HDL? Or is there some magic way to do this that I'm too tired to figure out?

[Altera_Forum]

HDL isn't much trouble for what you're trying to do. All you need is a black box of the design with just the port names and port directions (for example, an empty module in Verilog with just the port list). You can mix that method for your big buses with Reserve Pin assignments for other pins if you want, but I'd use the black box HDL file to tell Quartus all the pin names and directions. 

 After creating the black box HDL file, Analysis & Elaboration is enough to access the pin names in the Pin Planner. After the pin locations and I/O standards are entered, run Analysis & Synthesis and I/O Assignment Analysis.  Later you can start adding things like PLLs to the HDL file to tell Quartus what is happening on clocks for more thorough checks of pin placement restrictions. You can add some dummy logic to keep the clocks from synthesizing away, or you can add black box HDL placeholders for the lower-level blocks of the design and use incremental compilation empty design partitions for them until you're ready to write the real HDL for those blocks.    If you still prefer Reserve Pin assignments, set up the Assignment Editor window with one example entered. Do "File --> Export" to create a .csv. Modify the spreadsheet in Excel to add rows for the rest of the pins. With the Assignment Editor window selected, do "Assignments --> Import Assignments".  If there's a trick to do what you want with the Assignment Editor Edit bar, maybe someone will post that here.

[Altera_Forum]

You can use tcl script to add the pins' location and other properties of pins. For the other properties, I think you can select all the pins once and apply same property in the pin 

planner. But it looks like you need at least top level design file first.

[Altera_Forum]

Thanks for the responses. I typically do the HDL thing myself. The key to the question, however, was the "without HDL" part. Supposedly the whole point of the early pin planning with the "reserve pin" assignment was that you could do this without any HDL. Trying to do this without writing any HDL is convincing me that few people try pin planning this way. 

 The folks who design boards around here (and do much of the device selection) don't necessarily know HDL.  I did make a bit more progress today. If you enter an assignment like "mybus[255..0]" in the assignment editor, the pin planner will then show all the "mybus[0]", "mybus[1]", ..., "mybus[255]" in the all pins box - allowing you to start drag & dropping them individually onto the chip image. However, the assignment editor behaves oddly with the "mybus[255..0]" assignment - it stays yellow and sometimes doesn't give you the pull-down options in the "assignment" or "value" columns.