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Embedded constraints

Altera_Forum
Honored Contributor II
‎07-16-2014 09:49 AM
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Hello. Using altera_attribute I am trying to place constraints in Verilog source. The exact line is: 

(* altera_attribute = "-name SDC_STATEMENT \"create_clock -name clk143 -period 7.0 \"" *) 

No luck, after compilation the clock is set to default 1000MHz. What could be wrong? Quartus v11.1 64-bit
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Altera_Forum
Honored Contributor II
‎07-16-2014 01:34 PM
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I don't do Verilog, but it looks like you need double double quotes around the SDC statement. 

Also look here: http://www.alteraforum.com/forum/showthread.php?t=43886
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