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Altera_Forum
Honored Contributor I
2,461 Views

Encoder for dsd audio stream in SDIF-3 format, VHDL - help a newbie

Hello folks, 

 

I'm a newbie in VHDL programming. 

I'm trying to achieve SDIF-3 encoding from a dsd datastream coming off from an A-D conversion chip.  

The dsd stream from the chip features two independent channels (L&R) data flow, plus a bitclock line. 

 

 

The SDIF-3 coding scheme (see pic below), states that the channel coding splits each original bit in a 2 'semi-bit' pattern, by double the original bitclock rate.  

IE: if the original bit on the source is '0', the pattern must include the original value+it's inverted, so '0-1',  

if the bit value of the source stream is '1', the pattern is '10', and so on... 

 

 

I was thinking of using a double-edge triggering to do the frequency doubling of the output stream, so that at the rising edge, the encoder outputs the first semi-bit value, then on the falling edge, the encoder outputs the inverted semi-bit to complete the pattern. 

 

 

Please see the image attached below about the official coding scheme for this format. 

 

 

I'm not sure if the code is correct, even if it is possible to do it that way. 

 

 

Unfortunately I have lack of knowledge on how to simulate this.  

Any help, suggestion, greatly appreciated. My code attached... 

 

Thank you in advance! :)
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12 Replies
Altera_Forum
Honored Contributor I
177 Views

I highly suggest you find a tutorial on how to do simulation. There are plenty out there.

Altera_Forum
Honored Contributor I
177 Views

Thank you for the quick reply. 

Unfortunately my code cannot be synthesized. I get the following error: 

"[Synth 8-27] nested clocked statements not supported [encoder1.vhd":27] 

 

What I wanted to get was: at rising edge, the first semi-bit of pattern, at the falling edge, the second semi-bit (inverted) of pAttern. 

Is there a better way to do it? 

 

If you can help, that would be fantastic. 

My code is attached to my first message. 

 

Thanks.
Altera_Forum
Honored Contributor I
177 Views

 

--- Quote Start ---  

Thank you for the quick reply. 

Unfortunately my code cannot be synthesized. I get the following error: 

"[Synth 8-27] nested clocked statements not supported [encoder1.vhd":27] 

 

What I wanted to get was: at rising edge, the first semi-bit of pattern, at the falling edge, the second semi-bit (inverted) of pAttern. 

Is there a better way to do it? 

 

If you can help, that would be fantastic. 

My code is attached to my first message. 

 

Thanks. 

--- Quote End ---  

 

 

If you properly format you code you see immediately why: 

SENSE_CLK : process(clk) is begin if (clk'EVENT and clk = '1') then --detect source data @ rising edge q0 <= data_l; q1 <= data_r; if (clk'EVENT and clk = '0') then q0 <= not data_l; q1 <= not data_r; end if; end if; end process SENSE_CLK;  

Hint: try using an elsif 

Another hint: consider using a ddr output element
Altera_Forum
Honored Contributor I
177 Views

Thanks! ODDR primitive seems to do the trick, I have to find a way to simulate it. 

I'm planning to use this design on a CPLD, is the ODDR compatible with max ii/v ?
Altera_Forum
Honored Contributor I
177 Views

I am afraid that you will have to step up to MAX-10 to get DDR IO. 

I checked the MAX-V data-sheet/handbook and couldn't find a reference to DDR IO operation. 

I you want to use MAX-V (or MAX-II) you better use a clock with twice the bit-rate, which should pose no issue for SDIF-3 speeds
Altera_Forum
Honored Contributor I
177 Views

 

--- Quote Start ---  

I am afraid that you will have to step up to MAX-10 to get DDR IO. 

I checked the MAX-V data-sheet/handbook and couldn't find a reference to DDR IO operation. 

I you want to use MAX-V (or MAX-II) you better use a clock with twice the bit-rate, which should pose no issue for SDIF-3 speeds 

--- Quote End ---  

 

 

That was exactly what I thought in the very early days. Since the design features an external Master clock oscillator, which is used by the ADC chip as well, to derive it's DSD bit clock by dividing it, so thinking of doing the same for the double-data rate CLK to govern the CPLD global clock port, input the MCLK, then use CLKDIV2 for DSD128 (2x dsd), or CLKDIV4 for standard 1xDSD. 

 

I was thinking of using 2 DFFs, the first one providing the first non-inverted 'semi-bit, the second one for the inverted semi-bit. 

The thing is that I don't know how these 2 FFs can be put in succession to complete the pattern. 

 

Any hint? :confused: 

 

Thanks.
Altera_Forum
Honored Contributor I
177 Views

Hint: I recognise the SDIF-3 encoding as Manchester Encoding; so shake the google tree: "Manchester Encoding VHDL"

Altera_Forum
Honored Contributor I
177 Views

Thanks a lot! One thing that bugs me is that SDIF-3 seems to be the inverted of Manchester. 

From this paper (https://www.ijarcce.com/upload/2016/april-16/ijarcce%20114.pdf) the simplest way to implement a Manchester encoder is to XOR Din and Clkin to obtain '01' for a '1' from source, and '10' for a '0' source. 

Since sdif3 needs '10' for a '1' and '01' for a '0', will a simple replacement of XOR with an xnor do the trick? 

What are your thoughts?
Altera_Forum
Honored Contributor I
177 Views

 

--- Quote Start ---  

Thanks a lot! One thing that bugs me is that SDIF-3 seems to be the inverted of Manchester. 

From this paper (https://www.ijarcce.com/upload/2016/april-16/ijarcce%20114.pdf) the simplest way to implement a Manchester encoder is to XOR Din and Clkin to obtain '01' for a '1' from source, and '10' for a '0' source. 

Since sdif3 needs '10' for a '1' and '01' for a '0', will a simple replacement of XOR with an xnor do the trick? 

What are your thoughts? 

--- Quote End ---  

 

 

Beware of using combinatorial logic where the clock used to generate the other signals is used as a signal too; you may/will get issues with the small delays between the clock and the generated input signals which may/will result in an output with glitches. Using a double frequency clock to generate the output signal excludes that possible issue alltogether.
Altera_Forum
Honored Contributor I
177 Views

 

--- Quote Start ---  

Indeed I was thinking of using an external master clock as an input. It will run at a multiple of signal to generate, and clocks the source chip as well, so it must be in sync. 

 

Rewriting the new code doesn't appear to be working. It's not doing the pattern thing. 

What am I doing wrong? 

Please see attached the new code and a snap of the simulation.... 

--- Quote End ---  

 

 

Stay away from the XOR ... as I said oring it with a clock and then registering that with the same clock is fraught with possible issues; draw the timing diagram (carefully) and you will see why. 

Assume your clock is running at twice the bit-rate, and every '1'or '0' at the input lasts for 2 clock periods, you can write a (very simple) state machine to generate the correct code depending on the input received.
Altera_Forum
Honored Contributor I
177 Views

 

--- Quote Start ---  

Stay away from the XOR ... as I said oring it with a clock and then registering that with the same clock is fraught with possible issues; draw the timing diagram (carefully) and you will see why. 

Assume your clock is running at twice the bit-rate, and every '1'or '0' at the input lasts for 2 clock periods, you can write a (very simple) state machine to generate the correct code depending on the input received. 

--- Quote End ---  

 

Thanks! 

I changed the code following your suggestion. What I had in mind was treating the received input, output pattern forming register and output as 2-bit vectors, 

and using simple IF statements. 

However it doesn't seem to work. No pattern going on. 

New code and sim shot attached below. 

What am I doing wrong? :confused: 

 

Thank you!
Altera_Forum
Honored Contributor I
177 Views

Okay, I think I have something that probably works, I'm not sure if simulation is cheating me. 

With the new code, if Sim reset goes high at the falling edge, the encoder works fine, as you can see on sim1 pic attached. 

If reset goes high at the rising edge, the encoder does the pattern in reverse. (sim2 pic below). 

The CLK line is external, and runs at DDR, it's period is 10ns, so data period is 20ns. 

I've added a toggler to run the output at DDR, triggered at the rising edge. 

 

Is this a problem of simulation, what to do to make the encoder do the pattern right anytime? 

 

Any help appreciated!
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