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Hello guys !!
I'm working with an entity that has a 32 bits ouput and this entity is instantiated in my top_designì. My top_design has to ouput the 16 LSB ot this lower level entity. So i was wondering if it's possible to do something like: my_lower_lev_entity_inst : work.my_lower_lev_entity PORT MAP(......, ouput(15 downto 0)=> my_top_design_output) Is it a correct way ?? I see only a warning compiling th top in that way.. Thank you !Link Copied
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yes, you can select specific bits from a bus. If you leave the other bits unconnected, you will get a warning about "open" outputs being unconnected.
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Yep. thank you !

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