Error (10028): Can't resolve multiple constant drivers for net "z_mark[1]" at Modular

[Altera_Forum]

Hey guys! 

 We are a group of 4 people who are trying to compile the following vhdl program: LIBRARY ieee; USE ieee.std_logic_1164.all;  entity Mo_ex_4bit is  port (z: in std_logic_vector(7 downto 0);  Clock,Load: in std_logic;  y_out: out std_logic_vector(7 downto 0);  y_m,y_m1,y_m2,y_m3 : out std_logic_vector(1 downto 0);  done : out std_logic;   z_mark, y_mark, z_mark1, y_mark1, z_mark2, z_mark3, y_mark2, y_mark3:buffer std_logic_vector(1 downto 0);  y_b,z_b,m_b,y_b1,z_b1,m_b1, y_b2,y_b3,z_b2,z_b3,m_b2,m_b3: buffer std_logic_vector(1 downto 0);  exp: buffer std_logic_vector(7 downto 0)); end Mo_ex_4bit;  architecture struc of Mo_ex_4bit is   component Systolic_slice is  port (Clock: in std_logic;  y: in std_logic_vector(1 downto 0);  y_bitsh_in: in std_logic;  z: in std_logic_vector(1 downto 0);  z_bitsh_in: in std_logic;  m: in std_logic_vector(1 downto 0);  s_in: in std_logic_vector(1 downto 0);  qz,qy,bt: in std_logic;  y_bitsh_out: out std_logic;  z_bitsh_out: out std_logic;  s_out: out std_logic_vector(1 downto 0);  y_mark: out std_logic_vector (1 downto 0);  z_mark: out std_logic_vector (1 downto 0)); end component;  signal z_bitsh_out,y_bitsh_out: std_logic_vector( 3 downto 0); signal sum, s_in, s_out,s_out1,s_out2,s_out3: std_logic_vector(1 downto 0); signal y_mark_out,z_mark_out: std_logic; signal modeflipflop: std_logic;  begin process(Clock)  variable exponent_counter1, exponent_bit: INTEGER;   begin  if Clock'event and Clock='1' then    -- Initialising the start values  -- Only z is read from switches.  if Load='1'then   z_b(0)<= z(0); z_b(1)<= z(1);  z_b1(0)<= z(2); z_b1(1)<= z(3);  z_b2(0)<= z(4); z_b2(1)<= z(5);  z_b3(0) <= z(6); z_b3(1)<= z(7);  z_mark<= z_b ; z_mark1 <= z_b1; z_mark2<= z_b2; z_mark3 <= z_b3;  m_b(0)<='1'; m_b(1)<='0'; m_b1(0)<='1' ;m_b1(1)<='1'; m_b2(0)<='1' ; m_b2(1)<='0'; m_b3(0)<='1'; m_b3(1)<='0';     y_b(0)<='0'; y_b(1)<='0'; y_b1(0)<='0' ;y_b1(1)<='1'; y_b2(0)<='0' ; y_b2(1)<='1'; y_b3(0)<='1'; y_b3(1)<='1';     exp(0)<='1';exp(1)<='0';exp(2)<='1';exp(3)<='1';exp(4)<='1';exp(5)<='1';exp(6)<='1';exp(7)<='1';  exponent_counter1:= 0; exponent_bit:= 7 ;  end if;  if exponent_bit > -1 then   if exponent_counter1 < 9 then   modeflipflop<='0';  exponent_counter1:= exponent_counter1 + 1;   elsif exponent_counter1 < 17 then   modeflipflop<='1';  exponent_counter1:= exponent_counter1 + 1;  else   if exp(exponent_bit) = '1' then   y_b<= y_mark;y_b1<= y_mark1;y_b2<= y_mark2;y_b3<= y_mark3;  end if;   z_b<= z_mark;z_b1<= z_mark1;z_b2<= z_mark2;z_b3<= z_mark3;  exponent_counter1:= 0; exponent_bit:=exponent_bit-1;  end if;  else   done <= '1';  end if;  end if; end process; slice1: Systolic_slice port map (Clock,y_b,sum(0) and modeflipflop,z_b, sum(1)and modeflipflop, m_b, s_in , sum(1) and not modeflipflop,sum(0) and not modeflipflop ,z_mark_out,y_bitsh_out(0),z_bitsh_out(0), s_out, y_mark, z_mark); slice2: Systolic_slice port map (Clock,y_b1,y_bitsh_out(0),z_b1,z_bitsh_out(0), m_b1,s_out,sum(1) and not modeflipflop,sum(0) and not modeflipflop, z_mark_out,y_bitsh_out(1),z_bitsh_out(1),s_out1, y_mark1,z_mark1 ); slice3: Systolic_slice port map (Clock,y_b2,y_bitsh_out(1),z_b2,z_bitsh_out(1), m_b2,s_out1,sum(1) and not modeflipflop,sum(0) and not modeflipflop,z_mark_out,y_bitsh_out(2),z_bitsh_out(2),s_out2, y_mark2,z_mark2 ); slice4: Systolic_slice port map (Clock,y_b3,y_bitsh_out(2),z_b3,z_bitsh_out(2), m_b3,s_out2,sum(1) and not modeflipflop,sum(0) and not modeflipflop,z_mark_out,y_bitsh_out(3),z_mark_out,s_out3, y_mark3,z_mark3 ); y_out(0)<= y_b(0);y_out(1)<= y_b(1);y_out(2)<= y_b1(0);y_out(3)<= y_b1(1);y_out(4)<= y_b2(0);y_out(5)<= y_b2(1);y_out(6)<= y_b3(0);y_out(7)<= y_b3(1); y_m<= y_mark; y_m1<= y_mark1; y_m2<=y_mark2; y_m3<=y_mark3;  end struc; ******************************** but we keep getting an error saying Error (10028): Can't resolve multiple constant drivers for net "z_mark[1]" at Modular.  We cant find any solution to this according to what we need to redo in our program. We know that its because we have more than one drivers for all the z_mark buffers. The problem is that the z_mark buffers only has to be loaded once in the process in the initialisation, otherwise the driver should be driven by the concurrent statement.  Any suggestions to what we can change in the program?  Thanks in Advance and best regards group 38b at University of Southern Denmark.

[Altera_Forum]

Hi, 

 You are driving z_mark from two fronts - at least.   1): z_mark<= z_b ; z_mark1 <= z_b1; z_mark2<= z_b2; z_mark3 <= z_b3;  2) component instant 1

[Altera_Forum]

You can use intermediate signal and a construct: 

 temp1 <= z_b; -- driven by assignment temp2 <= ; -- driven by instant 1 z_mark <= temp1 ... or temp2 ....

[Altera_Forum]

Thanks for the fast reply's. It compiles now. We hope that it does what we expects it to do, otherwise we will post again. :) 

 We used the intermediate signal and it seems to work.  Best Regards 38b