Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Error (10137): Verilog HDL Procedural Assignment error at DE2_D5M.v(373): object "HEX5" on left-hand

Amerakim
Beginner
940 Views

i dont understand waht it means by it needing a variable data type. I tried declaring it as "reg [6:0] HEX5; " but still giving out the same error. May i know where i did wrong?

Amerakim_0-1673396304297.png

 

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Nurina
Employee
917 Views

Hi,


Is line 373 within an always block? Can you share this verilog code?


Thanks,

Nurina


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Nurina
Employee
883 Views

Hello,


Can you provide any updates?

I would need to have a look at the verilog file. Could you share it?

You may also share it through e-mail if it is confidential, I'm sending you an e-mail right now.


Thanks,

Nurina


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Nurina
Employee
869 Views

Hi,


We do not receive any response from you on the previous question/reply/answer provided. Please login to https://supporttickets.intel.com , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina


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