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Hello to anyone who is reading this thread. I'd like to know if there is anything wrong with this verilog code. I took this from one of the tutorials that I'm referring, but when I analyze this .v file Quartus keeps coming up with the Error (10170) on a few lines. The code is as attached (I couldn't copy and paste the code directly so I had to submit an attachment, sorry):
According to Quartus 9.1, the error appears on lines 20, 21, 24, 30, and 34 The error is something like this: Error (10170): Verilog HDL syntax error at serial.v(30) near text "'"; expecting ";" I can't quite figure what is the main problem, so any help would be greatly appreciated.Link kopiert
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You are using the wrong apostrophe in these lines where the error appears.
Instead of: ’ you have to use: '- Als neu kennzeichnen
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Thanks for pointing out the error. I'm obviously still a beginner on this language. There is another error but I think I know how to modify it to get it working.
Thanks again
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