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Error (10386): VHDL error : non-constant index is always outside the range


Hi folks,


I'm using Quartus II standard edition and I'm struggling to run successfully the synthesis of my design. The problem is the following, I have a signal (std_logic_vector type), which is indexed by a integer variable.


The SW insistes giving this error, but I know that the variable value does not exceed the range of the signal.


Piece of code where the error appears:

Declaration in the process:

      variable count                 : integer:= 1;

      variable aux_incomingMessage   : std_logic_vector ((512*N_BITS)-1 downto 0):= (others=> '0');


Inside the process:

 if short = '0' then

                       if count < 513 then

                           aux_incomingMessage((count*N_BITS)-1 downto (count-1)*N_BITS):= incomingMessage;

                           count:= count + 1;

I've read that Quartus had a bug in these type of usage of the integer variables. Is that already solved? How can I overcome this problems?


Thanks in advance for the answers,



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1 Reply
New Contributor II


I could reproduce your problem and found a possible solution.

You might want to check the indexes, but the basic idea is shown below.

architecture rtl of DE10_STD_FORUM is   constant N_BITS : integer:=8; -- declare -- signal test_incomingMessage : std_logic_vector (N_BITS-1 downto 0):= (others=> '0'); signal aux_incomingMessage : std_logic_vector ((512*N_BITS)-1 downto 0):= (others=> '0');   begin   -- body -- process (CLOCK2_50) variable count : integer:= 1; variable index : natural range 4096 downto 0; begin if rising_edge(CLOCK2_50) then if count < 513 then index:=count*N_BITS; aux_incomingMessage(index-1 downto index-N_BITS)<= test_incomingMessage; count:= count + 1; end if; end if; end process; end rtl;


Best Regards,