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I am in trouble in VHDL analyze & synthesis.
I use "Quartus Prime Verion 15.1.0 Build 185 10/21/2015 SJ Lite Edition". It defines the function in the package. One of them there is no argument. sample_code.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Sample_Code is
subtype Code_Type is std_logic_vector(3 downto 0);
type Code_Vector is array (integer range <>) of Code_Type;
function New_Code(DATA:std_logic_vector) return Code_Type;
function New_Code(DATA:unsigned ) return Code_Type;
function New_Code(DATA:integer ) return Code_Type;
function New_Code return Code_Type;
end Sample_Code;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package body Sample_Code is
function New_Code(DATA:std_logic_vector) return Code_Type is begin
return DATA(Code_Type'range);
end function;
function New_Code(DATA:unsigned ) return Code_Type is begin
return New_Code(std_logic_vector(DATA));
end function;
function New_Code(DATA:integer ) return Code_Type is begin
return New_Code(to_unsigned(DATA, 4));
end function;
function New_Code return Code_Type is begin
return New_Code(0);
end function;
end Sample_Code;
I call no-argment function by <package_name>.<function_name> sample_1_ng.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Sample_Code;
entity Sample is
port (O: out Sample_Code.Code_Type);
end Sample;
architecture RTL of Sample is
begin
O <= Sample_Code.New_Code;
end RTL;
then error occured when Analyze & Synthesis --- Quote Start --- Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition Info: Processing started: Sat Feb 06 00:10:09 2016 Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition Info: Processing started: Sat Feb 06 00:10:09 2016 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sample_altera -c sample_altera Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 2 design units, including 1 entities, in source file sample_1_ng.vhd Info (12022): Found design unit 1: Sample-RTL Info (12023): Found entity 1: Sample Info (12022): Found design unit 1: Sample-RTL Info (12023): Found entity 1: Sample Info (12021): Found 2 design units, including 0 entities, in source file sample_code.vhd Info (12022): Found design unit 1: Sample_Code Info (12022): Found design unit 2: Sample_Code-body Info (12022): Found design unit 1: Sample_Code Info (12022): Found design unit 2: Sample_Code-body Error (10404): VHDL error at sample_1_ng.vhd(10): can't determine object and type associated with indexed name or signature name near text "New_Code" -- found 4 possible objects and types Info (10797): VHDL info at sample_code.vhd(7): first match for 'New_Code' found here Info (10797): VHDL info at sample_code.vhd(8): another match for 'New_Code' found here Info (10797): VHDL info at sample_code.vhd(9): another match for 'New_Code' found here Info (10797): VHDL info at sample_code.vhd(10): another match for 'New_Code' found here Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 855 megabytes Error: Processing ended: Sat Feb 06 00:10:34 2016 Error: Elapsed time: 00:00:25 Error: Total CPU time (on all processors): 00:01:01 Error: Peak virtual memory: 855 megabytes Error: Processing ended: Sat Feb 06 00:10:34 2016 Error: Elapsed time: 00:00:25 Error: Total CPU time (on all processors): 00:01:01 --- Quote End --- but, I call no-argment function by <function_name> only, then no problem. sample_1_ok.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Sample_Code.all;
entity Sample is
port (O: out Code_Type);
end Sample;
architecture RTL of Sample is
begin
O <= New_Code;
end RTL;
why? By the way, in Xilinx Vivado this problem does not occur.
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3 Replies
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I don't see keyword ALL after USE work.Sample_Code in the 1st section but it presents in the 2nd. Try also with USE work.all
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Looks like a bug - report it to altera.
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Thank you. It was reported to Altera's Service Request.
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