Error (10430): VHDL Primary Unit Declaration:already exists in library "work"

Altera_Forum · ‎06-24-2011

Hi all,

in QuartusII web edition, I tried to compile a simple VHDL project and the result is this error message:

error (10430): vhdl primary unit declaration error at clk_div.vhd(56): primary unit "clkdiv" already exists in library "work"

this is my simple project:

 
library IEEE;
use IEEE.std_logic_1164.all;
entity CLKDIV is
    generic
    (
        constant M : integer:=1
    ); -- generic
    port
    (
        reset_i, ref_clk_i, clk_i : in std_logic;
        clk_o, en_o : out std_logic
    ); -- port
end CLKDIV;
architecture CLKDIV_ARCH of CLKDIV is
    signal OutputVal : std_logic;
begin
    MainProcess : process(reset_i, ref_clk_i)
        variable oldClkVal      : std_logic;
        variable nPeriodsCount  : integer range 0 to M-1;
        variable fSync          : boolean;
    begin
        if reset_i='1' then
            oldClkVal:='0';
            nPeriodsCount:=0;
            fSync:=false;
            OutputVal<='0';
            en_o<='0';
        elsif rising_edge(ref_clk_i) then
            en_o<='0';
            if (clk_i/=oldClkVal and fSync) or (clk_i='1' and oldClkVal='0') then
                fSync:=true;
                if nPeriodsCount=0 then
                    if OutputVal='0' then
                        en_o<='1';
                    end if;
                    nPeriodsCount:=M-1;
                    OutputVal<=not OutputVal;
                else
                    nPeriodsCount:=nPeriodsCount-1;
                end if;
            end if;
            oldClkVal:=clk_i;
        end if;    
    end process MainProcess;
 
    clk_o<=OutputVal;
 
end CLKDIV_ARCH;

where am I going wrong?

Altera_Forum · ‎06-24-2011

there is another file with an entity in it called CLKDIV in the project.

Altera_Forum · ‎06-24-2011

Ok, so I have to delete that file from the project directory?

Is that directory named "work" in quartus, even if it has another name in my PC?

Altera_Forum · ‎06-24-2011

Instead of deleting it, I would find out where the other CLKDIV is. How do you know another entity isnt using CLKDIV, and which one should it use?

Work is just the working library in the VHDL source. There isnt neccessarily a directory called work.

Altera_Forum · ‎06-24-2011

ok, thanks

Altera_Forum · ‎06-24-2011

I solved the problem, but now in this project there is another error:

critical warning: synopsys design constraints file file not found: 'clkdiv.sdc'. a synopsys design constraints file is required by the timequest timing analyzer to get proper timing constraints. without it, the compiler will not properly optimize the design.

Have I to create a .sdc file?

Altera_Forum · ‎06-24-2011

You dont have to create one. Without it, it will just tell you the max speed that each clock could theoretically run at. If you specify clock constraints, it can make the fitter work harder to actually acheive timing.

Altera_Forum · ‎06-24-2011

Ok, I've almost finished, I only have to solve some last problems :)

Now I have this error, regarding TimeQuet:

error: can't run timequest timing analyzer (quartus_sta) -- fitter (quartus_fit) failed or was not run. run the fitter (quartus_fit) successfully before running the timequest analyzer (create_timing_netlist).

Where am I going wrong?

Altera_Forum · ‎06-24-2011

Id have thought that error is fairly obvious.

Either you didnt run the fitter or there was a fit error.