Error 10500

Altera_Forum · ‎04-08-2011

I'm trying to make a magnitude comparator in VHDL. When I try to compile it, I get:

"Error (10500): VHDL syntax error at mag_comp.vhd(15) near text "AGTB"; expecting ";"

I followed the directions and looked at line 15, but there isn't anything there that needs to be done.

Here's what I have typed out:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
    PORT ( a2, b2, a1, b1, a0, b0    :IN    STD_LOGIC;
            AEQB, AGTB, ALTB        :OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
    PROCESS (a2, b2, a1, b1, a0, b0)
        BEGIN
            IF (a2 > b2) THEN
            AEQB <= '0'
            AGTB <= '1'
            ALTB <= '0'
            ELSIF (a2 < b2) THEN
            AEQB <= '0'
            AGTB <= '0'
            ALTB <= '1'
            ELSE (a2 = b2) THEN
            AEQB <= '1'
            AGTB <= '0'
            ALTB <= '0'
            IF (a1 > b1) THEN
            AEQB <= '0'
            AGTB <= '1'
            ALTB <= '0'
            ELSIF (a1 < b1) THEN
            AEQB <= '0'
            AGTB <= '0'
            ALTB <= '1'
            ELSE (a1 = b1) THEN
            AEQB <= '1'
            AGTB <= '0'
            ALTB <= '0'
            IF (a0 > b0) THEN
            AEQB = '0'
            AGTB = '1'
            ALTB = '0'
            ELSIF (a0 < b0) THEN
            AEQB = '0'
            AGTB = '0'
            ALTB = '1'
END IF;
END PROCESS;
END behavior;

I'm not sure if I've done anything wrong, I'm kind of sketchy when it comes to VHDL.

Altera_Forum · ‎04-10-2011

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY mag_comp IS

PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC;

AEQB:OUT STD_LOGIC;

AGTB:OUT STD_LOGIC;

ALTB:OUT STD_LOGIC

);

END mag_comp;

Altera_Forum · ‎04-10-2011

You forgot a lot of end-of-line semicolons and a few closing 'end if;'

I'm don't think you can compare std_logic (<, >) except for equality (=, /=).