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Error (12061): Can't synthesize current design -- Top partition does not contain any

Altera_Forum
Honored Contributor II
9,661 Views

Hello people, 

 

I'm trying to compile the following code (below this paragraph) on Quartus II, I wrote the system verilog code on the altera modelsim program, there everything compiles and simulates without problems. When I try the compilation on Quartus II I receive the error: "Error (12061): Can't synthesize current design -- Top partition does not contain any logic"... I'm really new to this kind of language and to the software so if you guys could give me any help like you were teaching a children I would really apreciate... I'm trying to use quartus II to figure out how many logic ports and clock cycles I need to use for this mecanism I'm developing for my masters degree thesys. 

 

module DefRFID (); 

 

logic [31:0] r1; 

logic [31:0] r2; 

logic [31:0] r3; 

logic [31:0] ID; 

logic [31:0] K; 

logic [31:0] R1; 

logic [31:0] R2; 

logic [31:0] R3; 

logic [63:0] M1; 

logic [63:0] M2; 

logic [7:0] sbox1 [0:15][0:15]; 

logic [7:0] sbox2 [0:15][0:15]; 

logic [7:0] pchoice [0:15]; 

 

initial begin 

r1 = inicializarsboxesepchoice(); 

//teste2 = 20; 

ID = 32'b11110000111100001111000011110000; 

r1 = 32'b11110011110011110011110011110011; 

r2 = 32'b10100011110011110011110011110011; 

r3 = 32'b00110010010011110010010010010000; 

K = 32'b10010010010010011101101101101101; 

 

R1 = NLFSR(r1); 

M1 = {pertubationfunction(R1,r2),r2}; 

R2 = NLFSR(r2); 

M2 = {pertubationfunction(R2,r3),r3}; 

 

ID = NLFSR(ID); 

ID = pertubationfunction(ID,K); 

 

K = NLFSR(K); 

R3 = NLFSR(r3); 

K = pertubationfunction(K,((R3^R2)^R1)); 

 

 

$finish; 

end 

 

function logic [1:0] inicializarsboxesepchoice(); 

logic[1:0] retorno; 

retorno = 0; 

 

for(int i = 0; i < 16; i++) begin 

pchoice = 15 - i; 

for(int j = 0; j < 16; j++) begin 

sbox1[j] = i + j;  

end 

end 

 

for(int i = 0; i < 16; i++) begin 

for(int j = 0; j < 16; j++) begin 

 

sbox2[j] = sbox1[j];  

end 

end 

return retorno; 

endfunction 

 

function logic [31:0] NLFSR (logic [31:0] entrada);  

 

//$display ("Valor de entrada é %b", entrada); 

 

logic [31:0] r1ji; 

logic [31:0] retorno; 

logic [0:0] resultadologico; 

// $display ("Valor de entrada é %b", entrada); 

// $display ("Valor de r1ji é %b", r1ji); 

 

// $display ("Valor de entrada é %b", entrada); 

r1ji = entrada; 

 

for(int i = 0; i < 32; i++) begin 

resultadologico = (((((r1ji[0] ^ r1ji[2]) && r1ji[5]) ^ (r1ji[7] && r1ji[8])) ^ (( (r1ji[25] && r1ji[29])&& r1ji[13])^ r1ji[20])) ^ r1ji[16]); 

// $display ("Valor de resultadologico com r1ji %b é %b", r1ji,resultadologico); 

r1ji = r1ji >> 1; 

// $display ("Valor de r1ji após left shift é %b", r1ji); 

r1ji[31] = resultadologico; 

// $display ("Valor de r1ji após atribrlogico é %b", r1ji); 

for(int j = 0; j < 31; j ++) begin 

// $display ("Valor de r1ji[j] com j %d é %b", j,r1ji[j]); 

r1ji[j] = r1ji[j] ^ resultadologico; 

// $display ("Valor de r1ji após operação com j %d é %b", j,r1ji); 

end 

// $display ("Valor de r1ji na rodada %d é %b",i, r1ji); 

end 

retorno = r1ji; 

// $display ("Valor da saida NLFSR é %b", retorno); 

return retorno; 

endfunction 

 

function logic [15:0] calcsboxes (logic [7:0] Esbox1,logic [7:0] Esbox2); 

logic [15:0] retorno; 

logic [3:0] linha; 

logic [3:0] coluna; 

linha = Esbox1[7:4]; 

coluna = Esbox1[3:0]; 

// $display ("Valor de Esbox1 é %b", Esbox1); 

// $display ("Valor de linha é %d", linha);  

// $display ("Valor de coluna é %d", coluna); 

Esbox1 = sbox1[linha][coluna]; 

// $display ("Valor de Esbox1 é %d", Esbox1); 

linha = Esbox2[7:4]; 

coluna = Esbox2[3:0]; 

// $display ("Valor de Esbox2 é %b", Esbox2); 

// $display ("Valor de linha é %d", linha);  

// $display ("Valor de coluna é %d", coluna); 

Esbox2 = sbox2[linha][coluna]; 

// $display ("Valor de Esbox2 é %d", Esbox2); 

retorno = {Esbox1, Esbox2}; 

 

return retorno; 

endfunction 

 

function logic [15:0] calcpchoice (logic [15:0] Epchoice); 

logic [15:0] retorno; 

 

for(int i = 0; i < 16; i++) begin 

retorno = epchoice[pchoice]; 

end 

 

return retorno; 

endfunction 

 

function logic [31:0] pertubationfunction (logic [31:0] e1, logic [31:0] e2); 

logic [31:0] retorno; 

logic [15:0] L; 

logic [15:0] R; 

retorno = (e1 ^ e2); 

 

if((retorno[0] == 0) || (retorno[31] == 0)) begin 

L = retorno[15:0]; 

R = retorno[31:16]; 

 

end else begin 

L = retorno[31:16]; 

R = retorno[15:0]; 

end  

 

// $display ("Valor de L é %b", L); 

// $display ("Valor de R é %b", R); 

 

L = calcsboxes(L[15:8],L[7:0]); 

// $display ("Valor de L é %b", L); 

R = calcpchoice(R); 

// $display ("Valor de R é %b", R); 

retorno = {L,R}; 

return retorno; 

endfunction 

 

endmodule
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9 Replies
Altera_Forum
Honored Contributor II
5,946 Views
Altera_Forum
Honored Contributor II
5,946 Views

Thx for the quick reply, I will try this solution and see if it works... If it works i'll post here

Altera_Forum
Honored Contributor II
5,946 Views

The solution didn't work, the block was generated but the compilation gives the same error. Anyone has another sugestion?

Altera_Forum
Honored Contributor II
5,946 Views

I may be able to get to a computer tomorrow with the latest development tools so I can try to recreate your problem. What version of Quartus II are you using?

Altera_Forum
Honored Contributor II
5,946 Views

I'm using the version 12.0 (30 days trial), i've dowloaded it last week from altera website. A friend of mine is trying to help me, he said that my code is using too much "for"'s and "function"'s (too much high level programing)

Altera_Forum
Honored Contributor II
5,946 Views

I don't know a lot about Verilog, but it looks like your module doesn't have any output ports. Quartus synthesizer is quite smart, and if it sees the code you wrote won't generate any signal out of the FPGA, it will "optimize" it by taking averything away, as the functionnal result will be the same. So you should first make sure any results from your algorithm get one way or another to one or more FPGA pins. 

Second (but again I don't know a lot about Verliog) your code looks like a transcription of a software algorithm, and indeed it may result in a very complicated synthesized designed with lots of hardware in parallel. You will probably have to redesign a bit, add a clock signal and a sequencer to share resources over several clock cycles.
Altera_Forum
Honored Contributor II
5,946 Views

I was finally able to get to a computer with the latest tools and it turns out Daixiwen is correct regarding the need for output ports. As a test case I added a 32 bit output called "out" and assigned the value of "K" to that output in the initial process and the code compiles fine. 

 

The changes I made were: 

 

module DefRFID(testout); output testout; .... .... initial begin .... K = pertubationfunction.... out <= K;
Altera_Forum
Honored Contributor II
5,946 Views

Wow! Is it just that? Add the output and it works? I was startting to rework the whole code to make it more low level... I will try the changes you made and will get the results... One question which device family you used? (I don't have a clue which one I should use, I just chose a random one)

Altera_Forum
Honored Contributor II
5,946 Views

A couple of notes. 

1. You may need to do more than I did in order fully test your code. The synthesizer may still be "optimizing" away large portions of your code that don't drive any output. You need to make sure that all relevant outputs of your code are included as outputs of the module. If the signal "K" is dependent in some way on all other signals and processes and that is the final output you want to analyze then the changes I did should be fine. I'm thinking you may need to bring in a clock signal and register some of these processes (especially if number of clock cycles is something you are trying to evaluate) though honestly I haven't actually looked at what you are trying to do here. 

2. Depending on the results you get it may still be a good idea to rework your code to a lower level. 

3. I chose a mid-grade Cyclone IV device. No particular reason other than I was sure it would easily fit your module.
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