In attach two project - completely identical, but
one made in Quartus 21.1 Standart and it is synthesized,
second made in Quartus 21.1 PRO - the synthesis is not completed due to an error
we need to work with Cyclone 10 GX using such constructions - how to solve this problem ?
Good afternoon again, Intel !
In first message i made one mistake - used version Quartus 20.1.1 Standart - last version.
Ok, this is really important to us - we decided to take the aligned versions - Pro, Standard and Lite - release 20.1, Release date: June, 2020
The situation is completely similar - Standard and Lite working well, Pro stopped with error - projects in attachment.
As I wrote above, this is an important problem for us - what solution do you recommend ?
Sorry for the late reply. After checking, the error is due to quartus_syn switch from MCFU (Multiple File Compilation Unit) to SFCU (Single File Compilation Unit) for SystemVerilog files in Quartus Pro. This causes the enum to be defined twice in two separate compilation units (files) when the .svh header is included in the two separate files.
There is two workaround that you can use.
1. The easier one is to insert line below in the project .qsf file.
set_global_assignment -name VERILOG_CU_MODE MFCU
2. You can fix this problem by declaring and importing packages. You can include the svh file once in one of your files and simply import the package in all the other files where you need the enum definition. Attached the modified test case that you provided previously.
Attached information on Intel Quartus Prime Pro Edition follows the SFCU method:
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.