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Error 19724: not enough LAB's for clock region

PVanL
Novice
114,914 Views

Dear Support, i have this error Error(19724): Fitter requires 628 LABs for clock region in locations from lower-left (13, 32) to upper-right (37, 58), but only 621 LABs are available exclusively for that region

I tried some suggestions i found on the forum without succes.

I cannot find how to use the statements

  • set_instance_assignment -name CLOCK_REGION -to <to> -entity <entity name><value>
  • set_instance_assignment -name CLOCK_REGION -from <from> -to <to> -entity<entity name> <value>,
  • set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "HIGH EFFORT", without succes,
  • and quartus does not accept:set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "OPTIMIZE FOR HIGH UTILIZATION",

I understand i have to enlarge the clock domain, but have no clue how to do this. I used this design with one channel on the cyclone10GX, which works fine, if i create a two channel version, Quartus reports this LAB error.

Please advice

See also

Place Stage Error(19724) on Arria 10 with Quartus Prime Pro 18.1

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9 Replies
VenTingT_Intel
Employee
114,865 Views

Hi PVanL,


You may try to use the Assignment Editor or by writing the command in QSF file to increase the size of the clock region.


Assignment Editor:

Go to Assignments > Assignment Editor, then in Assignment name column search for Clock Region and fill in other column details.

QSF file:

Open the QSF file and add the command you mentioned above to the QSF file.


Lastly, you may check out the following links to learn more about the clock region.

Cyclone10GX Clock Networks documentation:

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/clock-networks-and-plls-in-devices-revision.html 

Forum on solving the Error19724:

https://community.intel.com/t5/Programmable-Devices/Place-Stage-Error-19724-on-Arria-10-with-Quartus-Prime-Pro-18-1/m-p/1211774


Thanks.

Best Regards,

Ven Ting



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PVanL
Novice
114,850 Views

Hi Ven,

 

Thanks for answering, but this is what I found myself already. The issue is, I cannot find how to use the various commands.

Let me respond to your suggestions

 

1/ Go to Assignments > Assignment Editor, then in Assignment name column search for Clock Region and fill in other column details.

When I open Assignment editor, I get the following:

1

Ok

 

sfp0_txdisable

Virtual Pin

On

Yes

altera_eth_top

2

Ok

 

avalon_st_rxstatus_valid_156

Virtual Pin

On

Yes

altera_eth_top

3

Ok

 

avalon_st_rxstatus_data_156

Virtual Pin

On

Yes

altera_eth_top

4

Ok

 

avalon_st_rxstatus_error_156

Virtual Pin

On

Yes

altera_eth_top

5

Ok

 

csr_clk

I/O Standard

LVDS

Yes

altera_eth_top

6

Ok

 

ref_clk_clk

I/O Standard

LVDS

Yes

altera_eth_top

7

Ok

 

rx_serial_data[*]

I/O Standard

High Speed Differential I/O

Yes

altera_eth_top

8

Ok

 

tx_serial_data[*]

I/O Standard

High Speed Differential I/O

Yes

altera_eth_top

9

Ok

 

csr_clk

Input Termination

Differential

Yes

altera_eth_top

10

Ok

 

ref_clk_clk

Input Termination

Differential

Yes

altera_eth_top

11

Ok

 

ref_clk_clk(n)

Location

PIN_N23

Yes

   

12

Ok

 

ref_clk_clk

Location

PIN_N24

Yes

   

13

Ok

 

csr_clk(n)

Location

PIN_U23

Yes

   

14

Ok

 

csr_clk

Location

PIN_U24

Yes

   

15

Ok

 

rx_serial_data[0](n)

Location

PIN_F25

Yes

   

16

Ok

 

rx_serial_data[0]

Location

PIN_F26

Yes

   

17

Ok

 

tx_serial_data[0](n)

Location

PIN_G27

Yes

   

18

Ok

 

tx_serial_data[0]

Location

PIN_G28

Yes

   

19

Ok

 

rx_serial_data[1](n)

Location

PIN_H25

Yes

   

20

Ok

 

rx_serial_data[1]

Location

PIN_H26

Yes

   

21

Ok

 

tx_serial_data[1](n)

Location

PIN_J27

Yes

   

22

Ok

 

tx_serial_data[1]

Location

PIN_J28

Yes

   

23

Ok

 

master_reset_n

Location

PIN_AE4

Yes

   

24

   

<<new>>

         

So,. There is not a “clock region” mentioned.

If I enter “clock Region” under “assignment name”, I get “yes” under enabled, in Entity “altera_eth_top”. What next?

And if it would have been there, what should I have filled in?

 

2/ Open the QSF file and add the command you mentioned above to the QSF file.

As I mentioned, I do not know how to use those commands in the QSF file:

        1. I used set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "HIGH EFFORT", without succes
        2. quartus does not accept:set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "OPTIMIZE FOR HIGH UTILIZATION", (Quartus removes it from qsf file)
        3. I cannot find the syntax and parameters in set_instance_assignment -name CLOCK_REGION -to <to> -entity <entity name><value>
          I understand the syntax is something like -to “SX0 SY0 SX100 SY 100” (how to find the correct values?), and what are the values and syntax for <entity name> (is that “altera_eth_top”? or is that one of the entities below that?), and what is the value and syntax for <value>? I have no clue, and I cannot find it in a manual or example
        4. I cannot find the syntax and parameters in set_instance_assignment -name CLOCK_REGION -from <from> -to <to> -entity<entity name> <value>,  
          I understand the syntax is something like -to “SX0 SY0 SX100 SY 100” (how to find the correct values?), and what are the values and syntax for <entity name> (is that “altera_eth_top”? or is that one of the entities below that?), and what is the value and syntax for <value>? I have no clue, and I cannot find it in a manual or example
        5. In the *.fit.rpt and *.fit.place.rpt report you can find:

Error (19724): Fitter requires 646 LABs for clock region in locations from lower-left (13, 32) to upper-right (37, 58), but only 621 LABs are available exclusively for that region

Info (19797): The following node of the above-mentioned region failed to pack: "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_b66_decode|Decoder_9~16 "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_b66_decode|i30167~0" "dut_inst|CHANNEL[1].wrapper_lpi|locklink_topIC|b66_encode_ic|b66_enc_istore_ip|s_istore_fifo_cw[5].cw_lpi_stop" "dut_inst|CHANNEL[1].wrapper_lpi|locklink_topIC|b66_encode_ic|b66_enc_istore_ip|Select_1224~0" "dut_inst|CHANNEL[1].wrapper_lpi|locklink_topIC|ic_b66_decode|fsm2dpp_data[36]" Error (170025):

Fitter requires that more entities of type LAB be placed in a region than are available in the region File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

    Error (170026): Region "lower-left" corner: X13_Y32; Region "upper-right" corner: X37_Y58

    Info (170028): Region dimensions determined based on intersection of the following constraints: Promoted Clock Region

    Error (170029): The following resources need to be used in this region

    Error (18170): Fitter needs to use 646 out of 621 entities of type LAB in this region

    Info (170036): The following sample cells belong to the region being placed.

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[53]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[12]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[44]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[30].data64[44]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[41]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[20].data64[41]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[10]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[25]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[20].data64[25]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[26]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

(line 65 is a an array with 32 records, each with a vector data64 [63:0], sh [1:0] and a Boolean)

 

3/ Lastly, you may check out the following links to learn more about the clock region.

I have read that, but it does not explain how to repair this issue.

 

4/ Forum on solving the Error19724:

That is the link I gave to you, where the above suggestions under 2/ are given, but without guidance on how to use them

 

So, I hope you can give me more precise and elaborated help.

Thanks for your support.

 

Regards, Pieter

 

Summary says: (it looks as if there is plenty of room)….

Fitter Status : Failed - Wed Aug 24 12:38:27 2022

Quartus Prime Version : 20.2.0 Build 50 06/11/2020 SC Pro Edition

Revision Name : altera_eth_top

Top-level Entity Name : altera_eth_top

Family : Cyclone 10 GX

Device : 10CX220YF780E5G

Timing Models : Final

Power Models : Final

Device Status : Final

Total registers : 54903

Total pins : 29 / 340 ( 9 % )

Total virtual pins : 97

Total block memory bits : 292,672 / 12,021,760 ( 2 % )

Total RAM Blocks : 74 / 587 ( 13 % )

Total DSP Blocks : 1 / 192 ( < 1 % )

Total HSSI RX channels : 2 / 12 ( 17 % )

Total HSSI TX channels : 2 / 12 ( 17 % )

Total PLLs : 4 / 30 ( 13 % )

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VenTingT_Intel
Employee
114,831 Views

Hi Pieter,


Can you attach the project file? So that I can look into the issue clearer and assist you with that.


Thanks.

Best Regards,

Ven Ting


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PVanL
Novice
114,819 Views

Hi Ven,

Thanks for replying. I hope i attached the right files that will help you to identify the issue.

I modified them from e.g. name.qsf to name_qsf.txt, otherwise this tool does not accept them to be attached.

 

Hope you identify either the issue, or a workaround to get it working.

 

regards, pieter

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VenTingT_Intel
Employee
114,804 Views

Hi Pieter,


Thanks for attaching the files. However, can you archive your project, so that I can restore the complete project and ensure that no files are missing?


In Quartus, Open the project > Project > Archive Project.


Afterwards, you may upload the compressed .qar file. Thanks.


You may check out the link on archiving projects:

https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/archiving-projects.html 


Best Regards,

Ven Ting


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PVanL
Novice
114,757 Views

Hi Ven, is there a way to send you this compressed (can it be a zip as well?) on a private way to you, so that not the whole internet community is watching? ( i removed some stuff, hoping it would solve the problem, but that did'nt help)

Thanks, Pieter

 

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VenTingT_Intel
Employee
114,737 Views

Hi,


Kindly check your email box. I have sent you an email regarding this issue.


Thanks.

Best Regards,

Ven Ting


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VenTingT_Intel
Employee
114,688 Views

I’m glad that your question has been addressed through email, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

Best Regards,

Ven Ting

 

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey




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BC
Beginner
1,543 Views

Hello,

 

I am porting OpenCL Stratix 10 BSP onto 1SG1100 based custom board (instead of 1SG2800) from the stratix 10 development board bsp. I have successfully generated by flat bsp flow. However when switch to base bsp flow I am receiving 4 19724 errors from the fitter. I have updated clock region as SX0 SY0  SX6 SX7 as reported by the flat bsp flow as maximum (It was SX8 SX11 for the 1SG2800 which I did not change initially).  I am using Quartus 20.4.

 

The tail of the base fit.log is follows:

Info (11178): Promoted 15 clocks
Info (18386): freeze_wrapper_inst|board_kernel_reset_reset_n_reg (237 fanout) drives clock sectors (0, 0) to (6, 7)
Info (18386): board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|stratix10_altera_iopll_i|outclk[1] (7 fanout) drives clock sectors (0, 0) to (6, 7)
Info (18386): board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|stratix10_altera_iopll_i|outclk[0] (95249 fanout) drives clock sectors (0, 0) to (6, 7)
Info (18386): auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|atom_inst|atom (120 fanout) drives clock sectors (0, 0) to (3, 3)
Info (18386): board_inst|mem|mem_ddr4_s10|mem_ddr4_s10|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|core_clks_from_cpa_pri_nonabphy[0] (23145 fanout) drives clock sectors (0, 1) to (1, 7)
Info (18386): board_inst|pcie|pcie|hip|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|altera_xcvr_hip_channel_s10_ch0|altera_xcvr_pcie_hip_channel_s10_ch0|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|out_pld_pcs_tx_clk_out1_dcm (69655 fanout) drives clock sectors (0, 0) to (0, 7)
Info (18386): auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|intosc|clk (2404 fanout) drives clock sectors (0, 0) to (3, 1)
Info (18386): config_clk (2423 fanout) drives clock sectors (0, 0) to (1, 3)
Info (18386): board_inst|mem_0|mem_ddr4_s10|mem_ddr4_s10|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|core_clks_from_cpa_pri_nonabphy[0] (23139 fanout) drives clock sectors (0, 4) to (1, 7)
Info (18386): board_inst|mem|reset_controller_ddr4a|reset_controller_ddr4a|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (168 fanout) drives clock sectors (0, 4) to (0, 7)
Info (18386): board_inst|mem_0|mem_ddr4_s10|mem_ddr4_s10|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor (18 fanout) drives clock sectors (0, 4) to (0, 7)
Info (18386): pll_ref_clk (31 fanout) drives clock sector (0, 3)
Info (18386): board_inst|pcie|pcie|hip|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|altera_xcvr_hip_channel_s10_ch0|altera_xcvr_pcie_hip_channel_s10_ch0|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|out_pld_pcs_tx_clk_out2_dcm (4 fanout) drives clock sector (0, 0)
Info (18386): board_inst|mem|rst_controller_002|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (91 fanout) drives clock sector (0, 3)
Info (18386): auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|s10xcvrfabric|osc_clk_in_int (88 fanout) drives clock sector (0, 0)
Info (11888): Total time spent on timing analysis during Physical Synthesis is 0.00 seconds.
Info (170189): Fitter placement preparation operations beginning
Critical Warning: Compiling with slowed OpenCL Kernel clock. This is to help achieve timing closure for board bringup.
Info: Adding default timing constraints to JTAG signals. This will help to achieve basic functionality since no such constraints were provided by the user.
Info (19727): Fitter will now perform the packing at high effort level
Info (19727): Fitter will now perform the packing at the highest effort level
Error (19724): Fitter requires 32 LABs for |_3 region in locations from lower-left (11, 4) to upper-right (30, 291), but only 0 LABs are available exclusively for that region
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|pcie|pcie|dcore|dma_ctrl|rd_control|status_control_reg|rc_dma_addr_low[5]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|pcie|pcie|dcore|dma_ctrl|wr_control|status_control_reg|ep_dma_addr_low[5]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|mm_interconnect_15|dma_pr_reordering_buffer_0_s_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[11]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|mm_interconnect_15|dma_pr_reordering_buffer_0_s_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[10]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|pcie|pcie|dcore|sch|rx|rxhipif|dly0|dreg[164]"
Error (19724): Fitter requires 201 LABs for |_9_LOGIC_MODULE_0_10 region in locations from lower-left (12, 4) to upper-right (30, 291), but only 0 LABs are available exclusively for that region
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|kernel_ddr4a_bridge|board_mm_bridge_s10_0|rsp_readdata[1][431]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|kernel_ddr4a_bridge|board_mm_bridge_s10_0|rsp_readdata[1][422]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|kernel_ddr4a_bridge1|kernel_ddr4a_bridge1|rsp_readdata[1][73]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|kernel_ddr4a_bridge1|kernel_ddr4a_bridge1|rsp_readdata[1][68]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|mem_0|acl_hyper_optimized_ccb|acl_hyper_optimized_ccb|cmd_dcfifo|mem[22].wdata_m[7]"
Error (19724): Fitter requires 82 LABs for |_8 region in locations from lower-left (12, 40) to upper-right (30, 291), but only 0 LABs are available exclusively for that region
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|mem|mm_interconnect_0|agent_pipeline_001|gen_inst[0].core|data1[17]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|mem|mem_ddr4_s10|mem_ddr4_s10|arch|arch_inst|hmc.amm.amm.data_if_inst|amm_readdata_0[17]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|mem|mem_ddr4_s10|mem_ddr4_s10|arch|arch_inst|hmc.amm.amm.data_if_inst|amm_readdata_0[406]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|mem|mm_interconnect_0|agent_pipeline_001|gen_inst[3].core|data1[22]"
Info (19797): The following node of the above-mentioned region failed to pack: "board_inst|mem|mm_interconnect_0|mux_pipeline_001|gen_inst[1].core|data1[1]"
Error (19724): Fitter requires 1 LABs for |_11 region in locations from lower-left (11, 4) to upper-right (30, 147), but only 0 LABs are available exclusively for that region
Info (19797): The following node of the above-mentioned region failed to pack: "auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|jtag_hub_gen.real_sld_jtag_hub|mix_writedata[0]"
Info (19797): The following node of the above-mentioned region failed to pack: "auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|jtag_hub_gen.real_sld_jtag_hub|identity_contrib_shift_reg[0]"
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:09:19
Info (11888): Total time spent on timing analysis during Global Placement is 50.51 seconds.
Info (20274): Successfully committed placed database.
Error: An error occurred during placement
Error: Quartus Prime Fitter was unsuccessful. 5 errors, 73 warnings
Error: Peak virtual memory: 17560 megabytes
Error: Processing ended: Wed Dec 21 12:16:33 2022
Error: Elapsed time: 00:29:07
Error: System process ID: 10744
Info (19538): Reading SDC files took 00:00:17 cumulatively in this process.

 

Thank you for your time

Best regards

Bulent CANDAN

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