Error(20783): Open Drain option is set to 'ON' for pin I2C_AUDIO_SDA~pad, but setting is not support

[paul26]

Hi,

I tried to do a pass through logic for I2C . i have master and slave out side fpga and i need to connect that through fpga. SDA, SCL both are inout pins. So i added a tri state logic for this operation .The inout pin connect with a pin having I/O standard 3.3v LVCMOS. While compiling i got following errors.Can you please help me to fix this. Here with i am attaching the verilog code also

Error(20783): Open Drain option is set to 'ON' for pin I2C_AUDIO_SDA~pad, but setting is not supported by I/O standard 3.3-V LVCMOS.

code

inout I2C_AUDIO_SDA;
inout J_I2C4_DAT;

reg J_sda_inreg;
reg A_sda_inreg; 
always @(posedge fclk)

begin

    J_sda_inreg <= J_I2C4_DAT;

end

assign I2C_AUDIO_SDA = (!J_sda_inreg) ? 1'b0 : 1'bz;

always @(posedge fclk)

begin

    A_sda_inreg <= I2C_AUDIO_SDA;

end

assign J_I2C4_DAT = (J_sclk_inreg & !A_sda_inreg) ? 1'b0 :1'bz;

[paul26]

hi,

somebody please look on this issue.

[WZ2]

Hi there，

You assigned the open drain setting 'ON' to the specified I/O pin, but the specified I/O standard for this pin does not allow the specified setting.

Please re-assign your pin in <pin planner>, set your OD pin to a GPIO pin~

Best regards,

WZ

[FvM]

Hello,
Quartus infers open-drain outputs from the behavioural tri-state description in your code. With default "Auto Open-Drain Pins" synthesis settings, it generates dedicated open drain buffers, otherswise open-drain function is generated through IO-buffer output enable function. See below techology map snippets for comparison. According to device manuals, dedicated open-drain buffer (right side) involves speed advantage, for slow intefaces like I2C the difference is effectively irrelevant.

 

Thus you don't need to make specfic pin assignments.

There's however a different problem involved with your code. The intended pass-through logic doesn't work, it generates dead-lock situation between both pins, because you can't determine if a pin is driven low by the peer. 

Bidirectional I2C buffers with signal replication are using special analog hardware (modified Tx and Rx levels) or other methods of signal direction recognition to distinguish internal and external driven low state.

Regards
Frank

[WZ2]

Hi there,

Is there still question?

[WZ2]

Hi there,

I wanted to check if you have any further questions or concerns. If not, I will go ahead and mark this issue as resolved.

Additionally, we would greatly appreciate it if you could take a moment to fill out our survey. Your feedback is valuable to us and helps us improve our support quality.

Thank you for your time and cooperation.

Best regards,

WZ