Error(276001): Cannot synthesize dual-port RAM logic "..."

[alexislms]

Synthesis error:

Error(276001): Cannot synthesize dual-port RAM logic "...timestamps"

Code:

(*ramstyle="logic"*)logic [15:0][63:0] timestamps [CHANNELS] /*synthesis ramstyle="logic"*/;

How is that a dual-port RAM logic?!

verilog attribute + synthesis attribute, I can't do more to stop the bull**bleep** from that stupid tool.

Please advise.

[FvM]

Hello,
the type of inferred RAM is defined by the actual logic related to the memory object, not the synthesis attributes. Please show the relevant code.

Regards

Frank

[TingJiangT_Intel]

Hi there, is any progress on this issue.

[TingJiangT_Intel]

As we do not receive any response from you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.