Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Error Assigning binary literal to ufixed

Altera_Forum
Honored Contributor II
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Hi guys, 

 

I have been writing a ROM that I step through using a simple counter. Up until now the output of the ROM has been unsigned(9 downto 0), and assigning binary literals in the form "1111100000" has been working fine. 

 

However I decided that I might want to try with unsigned fixed point with the same total width as in the unsigned case ie ufixed(7 downto -2). see attached file... 

 

Now my understanding is that it shouldn't matter how the literals are assigned, so I haven't changed the literal values at all. 

 

However I get the following errors: 

 

Warning (12001): Port "oDAC_DATA[8]" does not exist in entity definition of "DDS_ROM". The port's range differs between the entity definition and its actual instantiation, "DDS_ROM:inst2". 

Warning (12001): Port "oDAC_DATA[9]" does not exist in entity definition of "DDS_ROM". The port's range differs between the entity definition and its actual instantiation, "DDS_ROM:inst2". 

Error (12009): Node "DAC_DB[9]" is missing source 

Error (12009): Node "DAC_DB[8]" is missing source 

Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 5 warnings 

Error: Peak virtual memory: 869 megabytes 

Error: Processing ended: Wed Jun 08 21:41:52 2016 

Error: Elapsed time: 00:00:20 

Error: Total CPU time (on all processors): 00:00:41 

Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 5 warnings 

 

 

Could someone please enlighten me as to where I may be going wrong please... 

thank you
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