Error: Can't simulate mismatched node types - Intel Community

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Error: Can't simulate mismatched node types

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Good day, I design ALU (arithmetic and logic unit) in the language of Verilog HDL. When I try to simulate the circuit though I get these errors:

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Warning: Wrong node type for node "result[0]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "result[1]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "result[2]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "result[3]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "result[4]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "result[5]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "result[6]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "result[7]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "flagZ" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "flagO" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Warning: Wrong node type for node "flagN" in vector source file. Design node is of type Output, but signal in vector source file is of type Input.

Error: Can't simulate mismatched node types

Error: Quartus II 64-Bit Simulator was unsuccessful. 11 errors, 11 warnings

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What am I doing wrong here?

P.S. I live in Russia, and does not know very well English. Forgive my ignorance.

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2,325 Views

I don't think so there is any problem in your source code.I think problem is in your test bench. So please provide your test bench.

I found one typo error in your source line 271.It should be z = (res == 0) ? 1 : 0 instead of z = (res=0) ? 1 : 0.

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