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Altera_Forum
Honored Contributor I
990 Views

Error: Cannot fit kernel(s) on device

​​Hello everyone, 

 

I want to implement some function of open source code with DE1SoC. 

 

The project uses opencl kernel to program the FPGA and have a host program to call the kernel. 

But when I build the project, there is an error said 'Error: Cannot fit kernel(s) on device'. While the host program and .aoco files were generated successfully. The details are as below: 

 

 

+--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 95% ; ; ALUTs ; 55% ; ; Dedicated logic registers ; 45% ; ; Memory blocks ; 84% ; ; DSP blocks ; 32% ; +----------------------------------------+---------------------------; aoc: First stage compilation completed successfully. Error: Cannot fit kernel(s) on device make: *** Error 1  

 

 

And the last several lines in the log file shows below (Seems there is no error?): 

2018.01.26.11:18:23 Info: border: "hps_io" instantiated altera_interface_generator "border" 2018.01.26.11:18:23 Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" 2018.01.26.11:18:23 Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" 2018.01.26.11:18:23 Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" 2018.01.26.11:18:23 Info: system: Done "system" with 93 modules, 244 files 

 

 

I have build the hello-word demo and boardtest demo successfully which are contented in the de1soc_opencl_v02.pdf (http://www.terasic.com.cn/attachment/archive/836/de1soc_opencl_v02.pdf). 

 

 

I use AOCL-16.1.0.196-windows and DE1 BSP for Altera SDK OpenCL 16.0. 

 

 

I totally have no idea about this problem. I have found very little solutions about this. 

 

 

Would you give me some suggestion? 

Thank you!
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2 Replies
Altera_Forum
Honored Contributor I
44 Views

Whatever design you've created is too big to fit in the FPGA. 

 

And the "error adapters" are not errors with your design. Sometimes they need to be added into the interconnect fabric for a system. The key issue is that your design is simply too big for the device.
Altera_Forum
Honored Contributor I
44 Views

For DE1SOC, I get Lane num = 8, and Vec Size = 4. Higher than that will result the error you have.

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