Error at Analysis and Synthesis step in Quartus 14.1 - (generic_pll primitive )

[Altera_Forum]

Hi, 

 when i am running my design in quartus 14.1 it is throwing error as -  Error (129037): Output port OUTCLK on atom "vip_example:sys|vip_example_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|vip_example_mem_if_ddr3_emif_0_pll0ll0|pll2_phy", which is a generic_pll primitive, is driving one or more illegal destinations   Error (129026): Output port OUTCLK of atom "vip_example:sys|vip_example_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|vip_example_mem_if_ddr3_emif_0_pll0ll0|pll2_phy" is driving the I input port of atom "ddr3_emif_0_pll_sharing_pll_mem_phy_clk~output", which is a cyclonev_io_obuf primitive. This connection is illegal   Info (129038): Input port INCLK of a cyclonev_phy_clkbuf primitive is a valid destination for output port OUTCLK on atom "vip_example:sys|vip_example_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|vip_example_mem_if_ddr3_emif_0_pll0ll0|pll2_phy"   Info (129038): Input port CLK of a cyclonev_ff primitive is a valid destination for output port OUTCLK on atom "vip_example:sys|vip_example_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|vip_example_mem_if_ddr3_emif_0_pll0ll0|pll2_phy"   Info (129038): Input port CLK of a cyclonev_dll primitive is a valid destination for output port OUTCLK on atom "vip_example:sys|vip_example_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|vip_example_mem_if_ddr3_emif_0_pll0ll0|pll2_phy"   Error (130005): When the OUTCLK port of a generic_pll primitive is driving out to the INCLK port of a cyclonev_phy_clkbuf it may not fanout to other destinations   what can be the issue?? i am not able to figure out.  PS - the design gives no issue during compilation when i run the same design on Quartus 13.0.

[Altera_Forum]

Hi, 

I have additionally created a small design and checked that the issue is device independent (in Quartus 14.1).  As far as i have gone through, the issue is with "ddr3 SDRAM controller with Uniphy". you may check at your end in order to confirm.