Error during compilation

[Altera_Forum]

Hello Friends, 

 I am compiling a project in Quartus 10.1SP1. The targeted chip is EP2AGX125DF25I3. It is giving me the following error - "Error: There is no valid device available". I am using the web-edition of Quartus. Are there some limitations in this and is the error due to this? When I change the device it is compiling correctly with no errors (but with warnings).  Can anyone advice me?  Regards, Vinod.

[Altera_Forum]

--- Quote Start ---  Hello Friends,  I am compiling a project in Quartus 10.1SP1. The targeted chip is EP2AGX125DF25I3. It is giving me the following error - "Error: There is no valid device available". I am using the web-edition of Quartus. Are there some limitations in this and is the error due to this? When I change the device it is compiling correctly with no errors (but with warnings).  Can anyone advice me?  Regards, Vinod.  --- Quote End ---    Hi,  the web edition supports only Arria II GX FPGAs: EP2AGX45, EP2AGX65.  Have a look to : http://www.altera.com/literature/po/ss_quartussevswe.pdf  Kind regards  GPK

[Altera_Forum]

Thank u very much indeed.

[Altera_Forum]

I thought the web edition supports all devices but generates only a time-limited programming file. This is an eye opener :)

[Altera_Forum]

hi every one  

i have a problem in compiling 4bit adder using vhdl in quartus 2 10.1 cyclone 2 ep2c35f672c6    Library ieee; Use ieee.std_logic_1164.all;  Entity 4bitadder is -- it is showing error here Port ( I0,I1 : in STD_LOGIC_VECTOR(3 downto 0); Cin : in STD_LOGIC; S : out STD_LOGIC_VECTOR(3 downto 0); Cout : out STD_LOGIC ); End 4bitadder;  Architecture arch of 4bitadder is -- it is showing error h  Component fulladder Port ( A,B,Cin : in std_logic; S,Cout : out std_logic ); End component;  Signal Temp : STD_LOGIC_VECTOR(2 downto 0);  begin  FA1: fulladder port map ( A => I0(0), B => I1(0), Cin => Cin, S => S(0), Cout => Temp(0) );  FA2: fulladder port map ( A => I0(1), B => I1(1), Cin => Temp(0), S => S(1), Cout => Temp(1) );  FA3: Fulladder port map ( A => I0(2), B => I1(2), Cin => Temp(1), S => S(2), Cout => Temp(2) );  FA4: fulladder port map ( A => I0(3), B => I1(3), Cin => Temp(2), S => S(3), Cout => Cout );  End arch; wheather i have to include 1 bit adder in this file or as an another file when using component instantiation please tell me that my errors are   Error (10500): VHDL syntax error at 4bitadder.vhd(4) near text "4"; expecting an identifier  Error (10500): VHDL syntax error at 4bitadder.vhd(14) near text "4"; expecting an identifier please help me as soon as possible.

[Altera_Forum]

VHDL identifiers can't start with a digit. Rename it to Adder4bit and you shouldn't have this error any more.