Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Error from Incremental Compilation

Altera_Forum
Honored Contributor II
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Hello All, 

 

I'm pulling my hair out trying to work out how I've managed to enable Incremental Compilation in the Web edition of Quartus 9.1sp1. Please see the picture. 

 

I believe this all happened when I added a SignalTap file to the project. I've trawled through the .qsf file and removed anything to do with SignalTap to no avail. 

 

Any help would be greatly appreciated. Brent.
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Altera_Forum
Honored Contributor II
638 Views

I've found this issue; it was caused when signal tap asked me if I'd like to 'set my netlist partition blah blah....' because I'd selected to tap nets that were post synthesis. I pressed yes without thinking. 

 

I also found that I missed a line on my qsf file that included a .dpf file in the project compilation. Removing this and all other references to partitions in my qsf has me going again.
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