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Hi,
I tried to to generate code for PLL with Megawizard plugin manager. I used multiply factor as 114 and division factor as 7. My input clock frequency is 16 MHz. When I compile the design, I get the following error: ----------- Error: Can't implement PLL "pll:pll_i|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone III PLL type Error: Can't implement clock multiplication and clock division parameter values for PLL "pll:pll_i|altpll:altpll_component|pll_altpll:auto_generated|pll1" Error: Can't implement PLL because Division and Multiplication cannot be achieved Critical Warning: Input frequency of PLL "pll:pll_i|altpll:altpll_component|pll_altpll:auto_generated|pll1" must be in the frequency range of 15.0 MHz to 15.99 MHz for locking Warning: Can't achieve requested value multiplication of 114 for clock output pll:pll_i|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] of parameter multiplication factor -- achieved value of multiplication of 244 ---------------- Is there something I am doing wrong? I thought i could generate PLL with any multiplication and division factor as long as it falls between 1 and 512. any help is appreciated. Thanks,Link Copied
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The requested VCO frequency is oustside the specified range of 600 to 1300 MHz. As a (somewhat dubious) workaround, you may want to specify an input frequency of 15.95 MHz.
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The PLL must find a least common multiple frequency for the VCO based on the input clock frequency and the mulitply/divide values (for all PLL outputs) that is in the range for the device (600 - 1300 MHz as pointed out by FvM).
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How do we know the VCO frequency? Is there a simple way to know that given my input clock frequency , multiply and divide factors?
I am only generating one output clock from this PLL. Thanks- Mark as New
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--- Quote Start --- How do we know the VCO frequency? --- Quote End --- It's displayed by the MegaWizard.
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Can I calculate by hand given Multiply, divide factors and input clock?

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