Error in Synthesis of ddr3 controller with a NiosII on StratixIV

[Altera_Forum]

Hi, 

I am getting the following error while running for StartixIV using Qaurtus2 9.1:  error: the datain input of delay chain primitive "altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_dp_io:dpio|altmemddr_0_phy_alt_mem_phy_dq_io:dqs_group[2].dq[5].dq_pad|gen_dq_input_with_deskeq.dqi_t1_delay" is driven by the o output of an i/o input buffer primitive that has too many fanout. when the datain input is driven by the o output of an i/o input buffer primitive, that output can only have one other fanout to a directin input of a half-rate input primitive.  This is a design with the NiosII processor, on chip memory and high performance II DDR3 controller. Any Suggestions?? -Sid

[Altera_Forum]

Hi, Sid. I have seen this error before, but it was awhile ago. I don't remember the exact cause, but I think it was one of two things. Either (1) the dq output (in your case, I think dq[5]) was not used and so synthesis deleted some logic, or (2) I specified the data mask (DM) signal as part of the dqs_group (in your case, dqs_group[2]) when, in fact, when I built the memory controller I had told the megawizard to not drive the DM pins. Sorry I can't be of more help.

[Altera_Forum]

Well...it turns out that it was a signal tap error. so I worked around it by removing the dq, dqs, dqsn and dm signals from signal tap. I then added the internal signals pointing to these signals to signal tap and it synthesized well. Also, there was another problem:- 

I was running all the tcl scripts before analysis and synthesis. Make sure to run only pin_assignment.tcl and the ddr_phy tcl script and "do not run" the auto_detect_pins tcl. -Sid