Error in case staement

[Altera_Forum]

I am trying to run a small code of VHDL on Quartus and it errors out saying 

error (10321): VHDL error at PPC_PCI_SM.vhd(499): choice ""10H"" overlaps with a previous choic error (10321): VHDL error at PPC_PCI_SM.vhd(499): choice ""00H"" overlaps with a previous choice Which is basically a "case" error  I have attached the relavant code too ,but strangely precision( a mentor tool) passes it..  clocked_state : PROCESS ( ppc_clk_66m,rst_N) variable wait_it_pci : natural range 0 to 5 ;  BEGIN  if (rst_N = '0') then  int_pci_dma_size <= SINGLE;  ppc_state <= PPC_IDLE;  wait_it_pci := 5 ;  ppc_read_brst <='0';  int_dma_access <= '0';  ta_read_N <= '1';  r_ta_read_N <= '1';  ta_write_N <= '1';  int_pci_busy <= '0';  int_eod <= '0';  int_aack_N <= '1';  ppc_req <= '0';  ppc_mtx_fifo_odd_wr <= '0';  ppc_mtx_fifo_even_wr <= '0';  ppc_mrx_fifo_odd_rd_1 <= '0';  ppc_mrx_fifo_even_rd_1 <= '0';  ppc_mrx_fifo_odd_rd_3 <= '0';  brst_counter <= "00000000";  int_ppc2pci_be <= (others => '0') ;  int_pci_address1_ppcclk <= (others =>'0');  ppc_pipe_stop_ppcclk <='0';  fifo_rst_a <= '0';  int_pci_error_ppcclk <= '0';  pci_error_ppcclk <='0';  elsif (ppc_clk_66m'EVENT AND ppc_clk_66m = '1') then  r_ta_read_N <= ta_read_N ;  if ( int_pci_error_ppcclk ='1') then  pci_error_ppcclk <='1';  end if ;  case ppc_state is  when PPC_IDLE=>  wait_it_pci := 5 ;  pci_error_ppcclk <='0';  ppc_read_brst <='0';  int_dma_access <= '0';  int_pci_error_ppcclk <= '0';  fifo_rst_a <= '0';  ppc_mtx_fifo_odd_wr <= '0';  ppc_mtx_fifo_even_wr <= '0';  ppc_mrx_fifo_odd_rd_1 <= '0';  ppc_mrx_fifo_odd_rd_3 <= '0';  ppc_mrx_fifo_even_rd_1 <= '0';  brst_counter <= "00000000";  int_pci_busy <= '0';  int_aack_N <='1';  ppc_pipe_stop if (ppc_start='1') then  case int_dma_size_mux is -- pour ganer une clk  when "110" => int_pci_dma_size <= EIGHT;  brst_counter <= EIGHT;  when "011" => int_pci_dma_size <= SINGLE;  brst_counter <= SINGLE;  when "111" => int_pci_dma_size <= DOUBLE;  brst_counter <= DOUBLE;  when "100" | "101" | "001" | "000"|"10H" | "00H" => int_pci_dma_size <= dma_wcount1;  brst_counter <= dma_wcount1;  when others => int_pci_dma_size <= (others =>'0');  brst_counter <= (others =>'0');  end case;  ppc_state <= PPC_WAIT;  ppc_req<= '1';  int_pci_busy <= '1';  -- brst_counter <= int_pci_dma_size;   if (int_pci_cmd(0)='0') then  ppc_pipe_stop_ppcclk <='1';

[Altera_Forum]

I don't know, what's the type of int_dma_size_mux, I guess std_logic_vector. If so "00H" is an alias for "001" and "10H" for "101". The case constants are existing twice, simply a VHDL syntax error. The error is probably ignored by the Precision tool, tha't the whole story. Or is there a different meaning of the said constants?

[Altera_Forum]

Oops You are right ,Its a std_logic_vector...:)

[Altera_Forum]

It's legal VHDL but questionable for synthesis. You can use '1', '0', 'Z', and sometimes 'X' (but only on the right-hand side of an assignment) but I'd avoid H and L altogether. These are meta-values that don't have any utility for a digital logic synthesis tool. They typically bit-encoded std_ulogic, so you only get 1/0 and hence the aliasing you're seeing.