Error: loop with non-constant loop condition must terminate within 250 iterations

[bitte929]

I am writing a test bench for a module and now I am getting this error, even though I have written a couple other test benches before it was all working fine but now I got this error,  please help me solve this

//Testbench

`timescale 1ns/1ps

`define HALF_CLOCK 10

`define SIMULATION_TIME 50000

`define RESET_TIME 300

module PulseCounter_tb();

//Var instantiation

logic tb_clk;

logic [7:0]tb_q;

logic tb_d;

logic tb_reset_n;

initial

begin //Clock making

tb_clk = 0;

forever

#`HALF_CLOCK tb_clk = ~tb_clk;

end

initial

begin //reset making

tb_reset_n = 1;

forever

#`RESET_TIME tb_reset_n=~tb_reset_n;

end

initial

begin //Input making

tb_d = 0;

forever

#130 tb_d = ~tb_d;

end

initial

forever //display output

#200 $display("%d",tb_q);

initial

#`SIMULATION_TIME $stop();

PulseCounter dut(.d(tb_d),

  .clk(tb_clk),

  .q(tb_q),

  .reset_n(tb_reset_n));

endmodule

[sstrell]

Does the error point to a line number?  What tool does this happen in?

There are no loops here with fixed iteration unless it's something in the PulseCounter.

[bitte929]

Points to line 18 i.e. (#`HALF_CLOCK tb_clk = ~tb_clk;)

Tool: Intel quartus prime 18.1 when I am writing a test bench

[sstrell]

Yeah, you can't compile a testbench like this in Quartus.  It has to be in your simulation tool.

[bitte929]

Yes I have already compiled some test benches on Model Sim Altera and it was working fine on the same PC but now all of a sudden this error popped up

[FvM]

Hi,

I see that the error is generated when you are compiling the testbench code in Quartus. This makes no sense, testbench must be compiled in simulator, e.g. Modelsim Altera Starter Edition shipped with Quartus 18.  

[bitte929]

yes I know but still it is throwing this error

[TingJiangT_Intel]

What's the detail error message, BTW Have you add the tb file to the project?

It may cause some problem when you compile tb with quartus.

[bitte929]

Yes I have added the tb file, I get the error once in a while and after some time its gone without me doing anything, no clue and the detailed error is already pasted above and nothing more to that

[FvM]

Presume you are still nonsensically trying to compile the project with testbench in Quartus?

[bitte929]

yes

I have a question, in one project I can still have multiple module files and multiple test benches right, provided I configure them properly on which one I want to execute.

[TingJiangT_Intel · Accepted solution]

You may try the following solution:

Description

This error may appear in the Quartus® II software when synthesis iterates through a loop in Verilog HDL for more than the synthesis loop limit. This limit prevents synthesis from potentially running into an infinite loop. By default, this loop limit is set to 250 iterations.

Resolution

To work around this error, the loop limit can be set using the VERILOG_NON_CONSTANT_LOOP_LIMIT option in the Quartus II Settings File (.qsf). For example:

set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 300

[bitte929]

Thank you

[FvM]

Do you expect that the "solution" will allow Quartus to synthesize the test bench code that causes the loop error?

forever

#`HALF_CLOCK tb_clk = ~tb_clk;

end

[WZ2]

Hi there,

This may be the related solution. You may try this solution, and let's check if it can be addressed.

[bitte929]

It worked thanks

[TingJiangT_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.