I got a pop-up problem report and no error shown in my err/warning console window. Not sure what is the cause. I think it has to do with assigning LVDS to my signal.
I did it as recommended by Intel-tech by defining only one single-ended signal call "OUT_P" and allow Pin planner to create the other diff signal. but it didn't work.
Here is a preview of the report: Not sure what to do.
Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op_place.cpp, Line: 1882gid != DEV_ILLEGAL_GLOBAL_IDFitter pre-processing
0x17cc63: FYGR_CDR_OP::place_atom_at_gid + 0x83 (fitter_fygr)
0x16777e: FYGR_CDR_OP::emulatedLVDS_placer + 0x55e (fitter_fygr)
0x2ab4c: FYGR_EXPERT::fitter_preparation + 0x6cc (fitter_fygr)
0x23860: FYGR_FITCC_FAMILY_EXPERT::fitter_preparation + 0x40 (fitter_fygr)
0x555b1: FITCC_EXPERT::fitter_preparation + 0x1f1 (FITTER_FITCC)
0x55f26: FITCC_EXPERT::invoke_fitter + 0x396 (FITTER_FITCC)
0x23af6: fygr_execute + 0x1a6 (fitter_fygr)
0xe8d0: fmain_start + 0x900 (FITTER_FMAIN)
0x41b1: qfit_execute_fit + 0x1bd (comp_qfit_legacy_flow)
0x5384: QFIT_FRAMEWORK::execute + 0x2a0 (comp_qfit_legacy_flow)
0x267f: qfit_legacy_flow_run_legacy_fitter_flow + 0x1c7 (comp_qfit_legacy_flow)
0x14410: TclInvokeStringCommand + 0xf0 (tcl86)
0x161e2: TclNRRunCallbacks + 0x62 (tcl86)
0x17a65: TclEvalEx + 0xa65 (tcl86)
0xa6f8b: Tcl_FSEvalFileEx + 0x22b (tcl86)
0xa5646: Tcl_EvalFile + 0x36 (tcl86)
0x12606: qexe_evaluate_tcl_script + 0x376 (comp_qexe)
0x11864: qexe_do_tcl + 0x334 (comp_qexe)
0x16755: qexe_run_tcl_option + 0x585 (comp_qexe)
0x380c3: qcu_run_tcl_option + 0x1003 (comp_qcu)
0x160aa: qexe_run + 0x39a (comp_qexe)
0x16e51: qexe_standard_main + 0xc1 (comp_qexe)
0x2233: qfit2_main + 0x73 (quartus_fit)
0x12e98: msg_main_thread + 0x18 (CCL_MSG)
0x1467e: msg_thread_wrapper + 0x6e (CCL_MSG)
0x16660: mem_thread_wrapper + 0x70 (ccl_mem)
0x12761: msg_exe_main + 0xa1 (CCL_MSG)
0x287e: __tmainCRTStartup + 0x10e (quartus_fit)
0x13033: BaseThreadInitThunk + 0x13 (KERNEL32)
0x71470: RtlUserThreadStart + 0x20 (ntdll)
OS name: Windows 10
OS version: 10.0
Quartus Prime Information
Address bits: 64
Edition: Lite Edition
- FPGA Design Tools
Once I change the "OUT_P" to I/O standard=2.5v from LVDS_E_3R and removed the "OUT_P(P) signal. I was able to Compile successfully.
But again when I change "OUT_P" back to LVDS, Pin planner will automatically create "OUT_P(P) ..... then Compile failed again.
Quartus doesn't display any error message except the pop-up report problem window
I try to install the latest version of Quartus-lite V18.1 but still, same issue.
Do you want to use Emulated-LVDS or true LVDS? The IO standard you have chosen is Emulated-LVDS (LVDS_E-3R). To use true LVDS, select LVDS standard in Pin planner and then try.
Hopefully, when you are setting these pins as LVDS make sure the rest of the single-ended signals assigned on the same bank are all using the same voltage setting, ie if using LVDS 2.5, then the bank should be set at 2.5V for all other signals.
Can you share your design here. To use LVDS IO , you may have to use the ALTLVDS_TX and ALTLVDS_RX megafunctions and then the output of this megafunctions should be given to the IO which should be set as LVDS type.