Re: Error: near "1e": Digits must follow 'E' character in real

Altera_Forum · ‎10-26-2016

Hello everyone,I'm a starter of Quartus II and I meet one question but I have no idea.

I want to creat *.vwf file to run functional simulation but it went wrong.The messages are as followed.

and I have uploaded my project files, because of limitation of file types, I rename their file names, you need to rename them again after downloading them.The real name are"mo60.bdf"&"m.vwf",and the project is about making a BCD counter of mod 60.


#  do mo60.do 
#  ** Warning: (vlib-34) Library already exists at "work".
#  
#  Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
#  -- Compiling module mo60
#  
#  Top level modules:
#      mo60
#  Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
#  -- Compiling module mo60_vlg_sample_tst
#  -- Compiling module mo60_vlg_check_tst
#  ** Error: mo60.vt(62): near "1": syntax error, unexpected INTEGER NUMBER, expecting ')'
#  ** Error: mo60.vt(92): near "1e": Digits must follow 'E' character in real.
#  ** Error: mo60.vt(93): near "2e": Digits must follow 'E' character in real.
#  ** Error: mo60.vt(94): near "3e": Digits must follow 'E' character in real.
#  ** Error: mo60.vt(95): near "4e": Digits must follow 'E' character in real.
#  ** Error: mo60.vt(246): near "1e": Digits must follow 'E' character in real.
#  ** Error: mo60.vt(246): near "2e": Digits must follow 'E' character in real.
#  ** Error: mo60.vt(246): near "3e": Digits must follow 'E' character in real.
#  ** Error: mo60.vt(246): near "4e": Digits must follow 'E' character in real.
#  ** Error: c:/altera/13.0sp1/modelsim_ase/win32aloem/vlog failed.
#  Executing ONERROR command at macro ./mo60.do line 4

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Altera_Forum · ‎10-26-2016

A .bdf file is a schematic file and not RTL. Maybe things have changed but I have never heard of Modelsim supporting .bdf files since you typically feed it RTL like verilog or VHDL. You might be able to use Quartus to convert your schematic bdf into verilog/VHLD and use that for your simulation instead.

Altera_Forum · ‎10-26-2016

It will be because you have outputs labelled as 1, 2 etc. HDL names cannot start with a number,.