Error while generating Nios V/g simulation model in Platform Designer

[ryangjoraas]

I am using Quartus Prime Lite version 23.1std.1 Build 993 on Windows 10 and I am getting an error message when I try to generate the Nios V/g simulation model.

The error message states that there is no such file '.../cadence/niosv_opcode_def.sv' in my Quartus installation directory.  I have tried to install Quartus Prime Lite twice already but it looks like it never installs the ../cadence/ directory.  I can see the 'aldec' and 'mentor' directories but no 'cadence' directory. 

Here is the error message that is in the report .txt file attached as well:

 Error: add_fileset_file: No such file C:/intelfpga_lite/23.1std/ip/altera/soft_processor/intel_niosv_g/cadence/niosv_opcode_def.sv
while executing
"add_fileset_file $current_sim/niosv_opcode_def.sv SYSTEM_VERILOG PATH $current_sim/niosv_opcode_def.sv $attr"
(procedure "fileset_callback_impl" line 83)
invoked from within
"fileset_callback_impl sim $entity_name"
(procedure "sim_callback" line 2)
invoked from within
"sim_callback cpu_system_cpu_hart"
Error: Generation stopped, 59 or more modules remaining
Error: qsys-generate failed with exit code 1: 2 Errors, 7 Warnings

Is there a fix for this?

[JingyangTeh]

Hi

I am Jingyang and will be helping you out in this case.

I tried generating the testbench for the Max10 and also got the same error.

Let me get back to you once I got the solution.

Regards

Jingyang, Teh

[JingyangTeh]

Hi

This is an expected behavior.

The generation of the testbench for NiosV simulation is not supported in the Windows Environment.

It is only supported for the Linux environment as mention in the table in the doc below:

1.8. EDA Interface Information (intel.com)

Regards

Jingyang, Teh

[ryangjoraas]

Hi, 

Thanks for the response. 

After looking at the table, I do have one last question:

Is there a way to generate the testbench only for Aldec Riviera-PRO but skip generating the testbench for Cadence so that this error would not occur?  

If so, what command would I use within Quartus Prime Lite version 23.1std.1 Build 993 on Windows 10 to do this?  

I ask these questions because I'm using Aldec Riviera-PRO and only need the testbench for this simulator.

Thanks, 

Ryan

[JingyangTeh]

Hi

'

There is no selection in Quartus however.

I think that the testbenches for Aldec is generated.

With the testbenches you could use the script in the "<project_directory>/sys_tb/sim/aldec"

to set up the simulation environment.

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any update on this case?

Are you facing any issue trying to run the simulation?

Regards

Jingyang, Teh

[ryangjoraas]

I have not tried running the simulation yet.
You can close this case however.

[JingyangTeh]

Hi

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh