Estimating design size in Quartus

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Estimating design size in Quartus

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Hello everyone,

I have a video feed that I need to send to a Leopard board and after calculations I estimate that I'll need around 11Mbits of memory. I've made a preliminary design, consisting of 256bits by 32768 word FIFO and 12 to 256 shift register. The design was compiled correctly but how do I get the info on how much space that it'll take if I were to upload it into an FPGA? (Say Stratix 3 for example?)

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