Expression has 8 elements, but must have 9 elements, and also, else null

Altera_Forum · ‎03-15-2016

Hi,

I have this variable, X, which is an std_logic_vector(8 downto 0).

I have inputs A,B,C which are std_logic_vector(7 downto 0). Also, a signal D which is also std_logic_vector(7 downto 0).

I also have a signal Z which is std_logic_vector(7 downto 0).

I need to add all the inputs and the signal into X and invert, so:

X := not(A+B+C+D);

At the end, I need to take the lower byte of X, so:

Z <= (X'length-2 downto 0);

I am getting an error with the X variable, but I'm not sure why. I understand that they both have different sizes, but when adding all these inputs/signals, it is very possible that due to the addition X will grow to 9 bits (maybe even more, thinking about it).

Anyway to solve this problem?

And a completely unrelated question... if I do something like:

if (condition) then
     do something;
else null;

Does it make the design more efficient/better or is it redundant and it's best to not use an else at all and just end the if statement?

Thanks!

Altera_Forum · ‎03-15-2016

first of all, you cannot do arithmatic with std_logic_vectors with standard VHDL - to do this you have to include non-standard packages, I assume you've used std_logic_unsigned (not part of the VHDL standard)

To do arithmatic you need to use numeric_std and used the signed/unsigned types instead.

When you do use a standard part for arithmatic (and the non-standard std_logic_signed/unsigned), none of them do bit growth for you - you need to handle that yourself by extending the inputs to the same length as the output before addition. There are two ways of doing this:

For unsigned, append a '0' at the MSB, or for signed, append the sign bit:

Unsigned:

X := ( '0' & A) +( '0' & B ) +( '0' & C) +( '0' & D);

Signed

X := ( A(A'high) & A) + ( B(B'high) & B ) + ( C(C'high) & C) + ( D(D'high) & D);

Or, using the standard library numeric std, you can use the resize function that works for signed or unsigned types:

X := resize(A, X'length) + resize(B, X'length) + resize(C, X'length) + resize(D, X'length);

For your second question, this is legal VHDL. But you have to consider that logic it will generate. If you have this code:


process(condition)
begin
  if condition then
    output <= ip;
  else 
    null;
  end if;
end process;

You are going to generate a latch because you are asking the output to hold it's value when the condition is false. But if you put it in a clocked process, you generate a register with an enable pin, but here the else case is redundant because you get the same behaviour with or without it:


process(clk)
begin
  if rising_edge(clk) then
    if condition then
      output <= ip;
    else
      null;  --redundant, because you get the same behaviour with or without the else case
    end if;
  end if;
end if;

This shows the inportance of understanding what logic your code is going to generate.

For synthesisable code, null is hardly ever used because of the redundancy or undesirable logic shown above. But it can be used to clarify that you explicity want to do nothing and havent just forgotten to fill the code it (for example wait states in a state machine).

Null does have far more uses in complex test benches, as it is the default value for pointers.

Altera_Forum · ‎03-15-2016

Thanks (again) for your comprehensive answer, Tricky. I did used the unsigned library, and I will try what you suggested.

As for the second question... do you have a recommendation on a good book/website on proper writing of VHDL code? I want to be able to write efficiently and understand the logic, like you said. A lot of times I run into logical errors and would love to really understand them and understand what I'm doing, because currently it seems like I'm just writing a piece of code and hoping to get it right.