- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi All,
I'm writing some DSP code, where the filter coefficients are parameterized, but fixed at instantiation time. I'm trying to keep the code generic to eliminate the need to import large lookup tables. To do this, I'm using the following constant function: function integer tap_sin; input integer tap; begin tap_sin= (tap == 0 ? 1 : $sin(PI*tap*TSAMP*BW)/(PI*tap*TSAMP*BW)) * $sin(2*PI*tap*TSAMP*FCENT) * (2*TSAMP*BW) * (2 ** 11); end endfunction When I try to compile this, I get: Error (10174): Verilog HDL Unsupported Feature error at ssb_bpf.v(41): system function "$sin" is not supported for synthesis Now, I know that $sin can't be synthesized, but I'm using it in a context where it should be evaluated during elaboration and turned into a constant. There is no need to synthesize the $sin function. Does anyone know of a way to do this cleanly, or is Quartus too rigid for this? thanks, MarcusLink Copied
5 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Marcus,
--- Quote Start --- Now, I know that $sin can't be synthesized, but I'm using it in a context where it should be evaluated during elaboration and turned into a constant. There is no need to synthesize the $sin function. Does anyone know of a way to do this cleanly, or is Quartus too rigid for this? --- Quote End --- In VHDL, I use functions like this to initialize constant's, and then those constants get used in the body of the code, i.e., inside process statements. Perhaps your Verilog needs some intermediate constants too. Its hard to tell without seeing the complete code. Cheers, Dave- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks Dave,
I tried something very basic, just to see if it was possible. Along the lines of: parameter foo = $sin(1); and it choked even on that. I don't know if there are compiler directives, or something else that tell Quartus to figure this out at elaboration.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- I tried something very basic, just to see if it was possible. Along the lines of: parameter foo = $sin(1); and it choked even on that. I don't know if there are compiler directives, or something else that tell Quartus to figure this out at elaboration. --- Quote End --- Does it work ok under Modelsim? (Just to confirm its not something else) Cheers, Dave
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
thanks for the fast reply!
Not modelsim, but iverilog. The code simulates fine, and generates the correct coefficients (correlated against matlab). Its just the synthesis that chokes. regards, Marcus- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Not modelsim, but iverilog. The code simulates fine, and generates the correct coefficients (correlated against matlab). Its just the synthesis that chokes. --- Quote End --- I'd be tempted to use iverilog to write out a file with the calculations, and then `include that file for synthesis. You could use a synthesis directive to switch between them, or a `define. A `define might be better, since you can then `include the file in iverilog after the first run has generated it. I know its not the best solution, but sometimes you just have to deal with Quartus the best you can :) Cheers, Dave

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page